View Z520_3107717.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

document number: 319535- 003us intel ? atom ? processor z5xx ? series datasheet ? for the intel ? atom ? processor z560 ? , z550 ? , z540 ? , z530 ? , Z520 ? , z515 ? , z510 ? , and z500 ? on 45 nm process t echnology june 201 0
2 datasheet information in this document is provided in connection w ith intel? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoe ver, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intel lectual property right. unless otherwise agreed in writing by intel, the intel products are not designed nor intended for any application in which the failure of the intel product could create a situation where personal injury or death may occur. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked ?reserved? or ?undefined.? intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the information here is subject to change without notice. do not finalize a design with this information. the products described in this docum ent may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the l atest specifications and before placing your product order. copies of documents which have an order number and are referenced in this document, or other intel literature, may be obtaine d by calling 1 - 800- 548- 4725, or by visiting intel's web site . ? intel processor numbers are not a measure of performance. processor numbers differentiate features within each processor family, not across different processor families. see http:// www.intel.com/products/processor_number for details. intel ? virtualization technology (intel ? vt) requires a computer system with an enabled intel ? processor, bios, virtual machine monitor (vmm) and, for some uses, certain platform software enabled for it. functionality, performance or other benefits will vary depending on hardw are and software configurations and may require a bios update. software applications may not be compatible with all operating systems. please check with your application vendor. hyper - threading technology requires a computer system with a processor support ing hyper - threading technology and ht technology enabled chipset, bios and operating system. performance will vary depending on the specific hardware and software you see. see h ttp://www.intel.com/technology/ hypertheading/ for more information including de tails on which processor supports ht technology. intel ? , intel ? atom tm , intel ? centrino ? , enhanced intel speedstep ? technology, intel ? virtualization technology (intel ? vt), intel ? thermal monitor, intel ? streaming simd extensions 2 and 3 (intel ? sse2 an d intel ? sse3), intel ? burst performance technology (intel ? bpt), intel ? hyper - threading technology (intel ? ht technology), and the intel logo are trademarks of intel corporation in the u. s. and other countries. *other names and brands may be claimed as th e property of others. copyright ? 2007 ? 201 0 intel corporation. all rights reserved .
datasheet 3 contents 1 introduction ...................................................................................................... 7 1.1 abstract ................................................................................................. 7 1.2 major features ....................................................................................... 7 1.3 terminology ........................................................................................... 9 1.4 refe rences ............................................................................................ 11 2 low power features .......................................................................................... 13 2.1 clock control and low - power states ........................................................ 13 2.1.1 package/core low - power state descriptions ................................ 15 2.2 dynamic cache sizing ............................................................................ 22 2.3 enhanced intel speedstep? technol ogy ................................................... 23 2.4 enhanced low - power states .................................................................... 24 2.5 fsb low power enhancements ................................................................. 25 2.5.1 cmos front side bus ................................................................ 25 2.6 intel? burst performance technology (intel? bpt) .................................. 26 3 electrical specifications ..................................................................................... 27 3.1 fsb, gtlref, and cmref ........................................................................ 27 3.2 power and ground pins ........................................................................... 27 3.3 de coupling guidelines ............................................................................ 28 3.3.1 v cc decoupling ......................................................................... 28 3.3.2 fsb agtl+ decoupling .............................................................. 28 3.4 fsb clock (bclk[1:0]) and processor clocking .......................................... 28 3.5 voltage identification and power sequencing ............................................. 28 3.6 catastro phic thermal protection .............................................................. 31 3.7 reserved and unused pins ...................................................................... 31 3.8 fsb frequency select signals (bsel[2:0]) ................................................ 31 3.9 fsb signal groups ................................................................................. 31 3.10 cmos asynchronous signals ................................................................... 33 3.11 maximum ratings .................................................................................. 33 3.12 processor dc specifications ..................................................................... 34 3.13 agtl+ fsb specifications ....................................................................... 45 4 package mechanical specifications and pin information .......................................... 47 4.1 package mechanical specifications ........................................................... 47 4.1.1 processor package w eight ......................................................... 47 4.2 processor pinout assignment ................................................................... 49 4.3 signal description .................................................................................. 56 5 thermal specifications and design considerations ................................................ 65 5.1 thermal specifications ............................................................................ 68 5.1.1 thermal diode ......................................................................... 68 5.1.2 intel? thermal monitor ............................................................. 70 5.1.3 digital thermal sensor .............................................................. 72
4 datasheet 5.1.4 out of sp ecification detection .................................................... 72 5.1.5 prochot# signal pin ............................................................... 72 figures figure 1. thread low - power states ..................................................................... 14 figure 2. p ackage low - power states ................................................................... 14 figure 3. deep power down technology entry sequence ....................................... 20 figure 4. deep power down technology exit sequence .......................................... 20 figure 5. exit latency table ............................................................................... 21 figure 6. active v cc and i cc loadline ..................................................................... 40 figure 7. deeper sleep v cc and i cc loadline ......................................................... 41 figure 8. package mechanical drawing ................................................................ 48 figure 9. pinout diagram (top view, left side) ..................................................... 49 figure 10. pinout diagram (top view, right side) ................................................. 50 tables table 1. references .......................................................................................... 11 table 2. coordinatio n of thread low - power states at the package/core level .......... 15 table 3. voltage identification definition ............................................................. 29 table 4. bsel[2:0] encoding for bclk frequency ................................................. 31 table 5. fsb pin groups .................................................................................... 32 table 6. processor absolute maximum ratings ..................................................... 34 table 7. voltage and current specifications for the intel? atom? processor z560, z550, z540, z530, Z520, and z510 ....................................................... 35 table 8. voltage and current specifications for the intel? atom? processor z500 ... 37 table 9. voltage and current specifications for the intel? atom? processor z515 ... 38 table 10. fsb dif ferential bclk specifications ...................................................... 42 table 11. agtl+/cmos signal group dc specifications ......................................... 43 table 12. legacy cmos signal group dc specifications ......................................... 44 table 13. open drain s ignal group dc specifications ............................................ 44 table 14. pinout arranged by signal name .......................................................... 51 table 15. signal description ............................................................................... 56 table 16. power specifications for intel? atom? processors z560, z550, z540, z530, Z520, and z510 ........................................................................ 66 table 17. power specifications for intel ? atom? processors z515 and z500 ............ 67 table 18. thermal diode interface ...................................................................... 69 table 19. thermal diode parameters using transistor model .................................. 69
datasheet 5 revi sion h istory document number revision number description revision date 319535 001 ? initial release april 2008 319535 002 ? update d information about intel ? atom processor s z515 and z550. ? added intel ? atom processor z550 specifications to table 7 ? changed vccboot value to vcclfm in table 7 and table 8. ? added n ew table 9, voltage and current specifications for inte l ? atom processor z515. ? removed emttm references as it is not a supported feature. march 2009 319535 003 ? added z560 information ? defeatured and removed mention of c6 split v tt june 2010
6 datasheet this page intentionally left blank.
introduction datasheet 7 1 introduction the intel ? ato m ? processor z5xx series is built on a new 45- nanometer hi - k low power micro - architecture and 45 nm process technology ? the first generation of low - power ia - 32 micro - architecture specially designed for the new class of mobile internet devices (mids). the int el atom processor z5xx series supports the intel ? system controller hub (intel? sch), a single - chip component designed for low - power operation. 1.1 abstract this document contains electrical, mechanical, an d thermal specifications for intel atom processors z5 60, z550 , z540 , z530 , Z520 , z515 , z510 , and z500 . note: in this document, intel atom processor z5xx series refers to the intel atom processor s z560, z550, z540, z530, Z520, z515, z510, and z500. note: in this document, the intel atom processor z5xx series is referred to as ?processor?. the intel ? system controller hub (intel? sch) is referred to as the ?intel? sch?. 1.2 major features the following list provides some of the key features on this processor: ? new single - core processor for mobile devices offering enhanced perfo rmance ? on die, primary 32 - kb instructions cache and 24 - kb write - back data cache ? 100- mhz and 133 - mhz source - synchronous front side bus (fsb) ? 100 mhz: intel atom processor z515, z510, and z500 ? 133 mhz: intel atom processor z560, z550, z540, z530 , and Z520. ? supports hyper - threading technology 2 - threads ? on die 512 - kb, 8 - way l2 cache ? support for ia 32 - bit architecture ? intel ? virtualization technology ( intel? vt) ? intel ? streaming simd extensions 2 and 3 ( intel ? sse2 and intel ? sse3) and supplemental streaming si md extensions 3 (ssse3) support ? supports new cmos fsb signaling for reduced power ? micro - fcbga8 packaging technologies ? thermal management support using tm1 and tm2 ? on die digital thermal sensor (dts) for thermal management support using thermal monitor (tm1 and tm2) ? fsb lane reversal for flexible routing ? supports c0/c1(e)/c2(e)/ c4(e) power states ? intel deep power down technology ( c6 ) ? l2 dynamic cache sizing ? advanced power management features including enhanced intel speedstep ? technology
introduction 8 datasheet ? execute disable bit support for enha nced security ? inte l? burst performance technology (intel? bpt) (intel atom processor z515 only)
introduction datasheet 9 1.3 terminology term definition # a ?#? symbol after a signal name refers to an active low signal, indicating a signal is in the active state wh en driven to a low level. for example, when reset# is low, a reset has been requested. conversely, when nmi is high, a non - maskable interrupt has occurred. in the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the ?#? symbol implies that the signal is inverted. for example, d[3:0] = ?hlhl? refers to a hex ?a?, and d[3:0]# = ?lhlh? also refers to a hex ?a? (h= high logic level, l= low logic level). front side bus (fsb) refer s to the interface between the processor and system core logic (also known as the i ntel ? sch chipset components). agtl+ advanced gunning transceiver logic is u sed to refer to assisted gtl+ signaling technology on some intel processors. intel? burst perfo rmance technology (intel? bpt) e nables on - demand performance, without impacting or raising mid thermal design point . bfm burst frequency mode cmos complementary m etal - oxide s emiconductor storage conditions refers to a non - operational state ?t he processo r may be installed in a platform, in a tray, or loose. processors may be sealed in packaging or exposed to free air. under these conditions, processor landings should not be connected to any supply voltages, or have any i/os biased , or receive any clocks. upon exposure to ?free air? ( that is , unsealed packaging or a device removed from packaging material) the processor must be handled in accordance with moisture sensitivity labeling (msl) as indicated on the packaging material. enhanced intel speedstep? te chnology technology that provides power management capabilities to low power devices. processor core processor core die with integrated l1 and l2 cache. all ac timing and signal integrity specifications are at the pads of the processor core. intel virtua lization technology processor virtualization which when used in conjunction with virtual machine monitor software enables multiple, robust independent software environments inside a single platform. tdp thermal design power v cc the processor core power supply . vr voltage regulator v ss the processor ground v cc hfm v cc at highest frequency mode (hfm) v cc lfm v cc at lowest frequency mode (lfm)
introduction 10 datasheet term definition v cc , boot default v cc voltage for initial power up v ccp agtl+ termination voltage v ccpc6 agtl+ termination volt age v cca pll supply voltage v ccdppwdn v cc at deep power down technology (c6) v ccdprslp v cc at deeper sleep (c4) v ccf fuse power supply i ccdes i ccdes for intel atom p rocessors z5xx series recommended design target power delivery (estimated) i cc i cc fo r intel atom p rocessors z5xx series is the number that can be use as a reflection on a battery life estimates i ah, i cc auto - halt i sgnt i cc stop - grant i dslp i cc deep sleep di cc /dt v cc power supply current slew rate at processor package pin (estimated) i cca i cc for v cca supply p ah auto halt power p sgnt stop grant power p dprslp deeper sleep power p dc6 deep power down technology (c6). t j junction temperature
introduction datasheet 11 1.4 references material and concepts available in the following documents may be beneficial w hen reading this document. table 1 . references document document number intel? system controller hub (intel? sch) datasheet http://www.intel.com/desi gn/chipsets/embedded/s chus15w/techdocs.htm intel? atom? processor z5xx series spe cification update http://www.intel.com/desi gn/chipsets/embedded/s chus15w/techdocs.htm intel ? 64 and ia - 32 architectures software developer's manuals volume 1: basic architecture http://www.intel.com/pro ducts/processor/ manuals/index.htm volume 2a: i nstruction set reference, a - m volume 2b: instruction set reference, n - z volume 3a: system programming guide volume 3b: system programming guide ap - 485, intel ? processor identification and cpuid instruction application note http://www.intel.com/d esi gn/processor/applnots/24 1618.htm
introduction 12 datasheet this page intentionally left blank.
low p ower features datasheet 13 2 low power features 2.1 clock control and low - p ower states the processor supports low power states at the thread level and the core/package level. thread states (tcx) loosely corres pond to acpi processor power states (cx). a thread may independently enter the tc1/autohalt, tc1/mwait, tc2, tc4, or tc6 low power states, but this does not always cause a power state transition. only when both threads request a low - power state (tcx) great er than the current processor state will a transition occur. the central power management logic ensures the entire processor enters the new common processor power state. for processor power states higher than c1, this would be done by initiating a p_lvlx ( p_lvl2 and p_lvl3) i/o read to the chipset by both threads. package states are states that require external intervention and typically map back to processor power states. package states for the processor include normal (c0, c1), stop grant and stop grant s noop (c2), deeper sleep (c4), and deep power down technology (c6). the processor implements two software interfaces for requesting low power states: mwait instruction extensions with sub - state hints and p_lvlx reads to the acpi p_blk register block mapped in the processor?s i/o address space. the p_lvlx i/o reads are converted to equivalent mwait c - state requests inside the processor and do not directly result in i/o reads on the processor fsb. the monitor address does not need to be setup before using the p_lvlx i/o read interface. the sub - state hints used for each p_lvlx read can be configured in a software programmable msr by bios. if a thread encounters a chipset break event while stpclk# is asserted, then it asserts the pbe# output signal. assertion of pbe# when stpclk# is asserted indicates to system logic that individual threads should return to the c0 state and the processor should return to the normal state. figure 1 shows the thread low - power states. figure 2 shows the package low - power states. table 2 provides a mapping of thread low - power states to package low power states.
low power features 14 datasheet figure 1 . thread low - power states c2 ? c0 stop grant core state break p_lvl2 or mwait(c2) c1/ mwait core state break mwait(c1) c1/auto halt halt break hlt instruction c4 ? / c6 core state break p_lvl4 or p_lvl6 ? mwait(c4/c6) stpclk# de-asserted stpclk# asserted stpclk# de-asserted stpclk# asserted stpclk# de-asserted stpclk# asserted halt break = a20m# transition, init#, intr, nmi, preq#, reset#, smi#, or apic interrupt core state break = (halt break or monitor event) and stpclk# high (not asserted) ? ? stpclk# assertion and de-assertion have no effect if a core is in c2 or c4. ? ? p_lvl6 read is issued once the l2 cache is reduced to zero. figure 2 . package low - power states dprstp# de-asserted dprstp# asserted snoop serviced snoop occurs stpclk# asserted stpclk# de-asserted slp# asserted slp# de-asserted dpslp# de-asserted dpslp# asserted stop grant snoop normal stop grant deep sleep ?? deeper sleep ? sleep ?? ? deeper sleep includes the c4 and c6 states ?? sleep and deep sleep are not states directly supported by the processor, but rather sub-states of silverthornes c4/c6
low power features datasheet 15 table 2 . coordination of thread low - power states at the package/core level thread 0 thread 1 tc0 tc1 1 tc2 tc4/tc6 t c0 normal (c0) normal (c0) normal (c 0) normal (c0) t c1 1 normal (c0) autohalt (c1) autohalt (c1) autohalt (c1) t c2 normal (c0) autohalt (c1) stop - grant (c2) stop - grant (c2) t c4/ t c6 normal (c0) autohalt (c1) stop - grant (c2) deeper sleep (c4)/deep power down (c6) note: autohalt or mwait/c1 to ent er a package/core state, both threads must share a common low power state. if the threads are not in a common low power state, the package state will resolve to the highest common power c - state. 2.1.1 package/core low - power state descriptions the following stat e descriptions assume that both threads are in a common low power state. for cases when only one thread is in a low power state no change in power state will occur. 2.1.1.1 normal states (c0, c1) these are the normal operating states for the processor. the proces sor remains in the normal state when the processor/core is in the c0, c1/autohalt, or c1/mwait states. c0 is the active execution state. 2.1.1.1.1 c1/autohalt powerdown state c1/autohalt is a low - power state entered when one thread executes the halt instruction whil e the other is in the tc1 or greater thread state. the processor will transition to the c0 state upon occurrence of smi#, init#, lint[1:0] (nmi, intr), or fsb interrupt messages. reset# will cause the processor to immediately initialize itself. a system ma nagement interrupt (smi) handler will return execution to either normal state or the autohalt powerdown state. see the intel ? 64 and ia - 32 architectures software developer's manuals, volume 3a/3b: system programmer's guide for more information. the system can generate a stpclk# while the processor is in the autohalt powerdown state. when the system de - asserts the stpclk# interrupt, the processor will return to the halt state. while in autohalt powerdown state, the processor will process bus snoops. the proc essor will enter an internal snoopable sub - state (not shown in figure 1 ) to process the snoop and then return to the autohalt powerdown state.
low power features 16 datasheet 2.1.1.1.2 c1/mwait powerdown state c1/mwait is a low - power state entered when one thread execute s the mwait(c1) instruction while the other thread is in the tc1 or greater thread state. processor behavior in the mwait state is identical to the autohalt state except that monitor events can cause the processor to return to the c0 state. see the intel ? 64 and ia - 32 architectures software developer's manuals, volume 2a: instruction set reference, a - m and volume 2b: instruction set reference, n - z , for more information. 2.1.1.2 c2 state individual threads of the dual - threaded processor can enter the tc2 state by in itiating a p_lvl2 i/o read to the p_blk or an mwait(c2) instruction. once both threads have c2 as a common state, the processor will transition to the c2 state ? however, the processor will not issue a stop - grant acknowledge special bus cycle unless the stpc lk# pin is also asserted by the chipset. while in the c2 state, the processor will process bus snoops. the processor will enter a snoopable sub - state described the following section (and shown in figure 1 ), to process the snoop an d then return to the c2 state. 2.1.1.2.1 stop - grant state when the stpclk# pin is asserted, each thread of the processors enters the stop - grant state within 1384 bus clocks after the response phase of the processor - issued stop - grant acknowledge special bus cycle. w hen the stpclk# pin is de - asserted, the core returns to its previous low - power state. since the agtl+ signal pins receive power from the fsb, these pins should not be driven (allowing the level to return to v ccp ) for minimum power drawn by the termination resistors in this state. in addition, all other input pins on the fsb should be driven to the inactive state. reset# causes the processor to immediately initialize itself, but the processor will stay in stop - grant state. when reset# is asserted by the sys tem, the stpclk#, slp#, dpslp#, and dprstp# pins must be de - asserted prior to reset# de - assertion. when re - entering the stop - grant state from the sleep state, stpclk# should be de - asserted after the de - assertion of slp#. while in stop - grant state, the proc essor will service snoops and latch interrupts delivered on the fsb. the processor will latch smi#, init#, and lint[1:0] interrupts and will service only one of each upon return to the normal state. the pbe# signal may be driven when the processor is in st op - grant state. the pbe# signal will be asserted if there is any pending interrupt or monitor event latched within the processor. pending interrupts that are blocked by the eflags.if bit being clear will still cause assertion of pbe#. assertion of pbe# ind icates to system logic that the entire processor should return to the normal state. a transition to the stop - grant snoop state occurs when the processor detects a snoop on the fsb (see section 2.1.1.2.2 ). a transition to the sleep state (see section 2.1.1.3.1 ) occurs with the assertion of the slp# signal.
low power features datasheet 17 2.1.1.2.2 stop - grant snoop state the processor responds to snoop or interrupt transactions on the fsb while in stop - gra nt state by entering the stop - grant snoop state. the processor will stay in this state until the snoop on the fsb has been serviced (whether by the processor or another agent on the fsb) or the interrupt has been latched. the processor returns to the stop - grant state once the snoop has been serviced or the interrupt has been latched. 2.1.1.3 c4 state individual threads of the processor can enter the c4 state by initiating a p_lvl4 i/o read to the p_blk or an mwait(c4) instruction. attempts to request c3 will also c overt to c4 requests. if both processor threads are in c4, the central power management logic will request that the entire processor enter the deeper sleep package low - power state using the sequence through the sleep and deep sleep states all described in the following sections. to enable the package level intel enhanced deeper sleep state, dynamic cache sizing and intel enhanced deeper sleep state fields must be configured in the pmg_cst_config_control msr. refer to section 2.1.1.3.3 for further details on intel enhanced deeper sleep state. 2.1.1.3.1 sleep state the sleep state is a low - power state in which the processor maintains its context, maintains the phase - locked loop (pll), and stops all internal clocks. the sleep s tate is entered through assertion of the slp# signal while in the stop - grant state and is only a transition state for intel atom processor z5xx series. the slp# pin should only be asserted when the processor is in the stop - grant state. slp# assertion while the processor is not in the stop - grant state is out of specification and may result in unapproved operation. in the sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. no transitions or assertions of signals (with the exception of slp#, dpslp#, or reset#) are allowed on the fsb while the processor is in sleep state. snoop events that occur while in sleep state or during a transition into or out of sleep state will cause unpredictable behavior. any tra nsition on an input signal before the processor has returned to the stop - grant state will result in unpredictable behavior. if reset# is driven active while the processor is in the sleep state, and held active as specified in the reset# pin specification, then the processor will reset itself, ignoring the transition through stop - grant state. if reset# is driven active while the processor is in the sleep state, the slp# and stpclk# signals should be de - asserted immediately after reset# is asserted to ensure the processor correctly executes the reset sequence. while in the sleep state, the processor is capable of entering an even lower power state, the deep sleep state, by asserting the dpslp# pin (see section 2.1.1.3.2 ). while the processor is in the sleep state, the slp# pin must be de - asserted if another asynchronous fsb event occurs.
low power features 18 datasheet 2.1.1.3.2 deep sleep state the deep sleep state is entered through assertion of the dpslp# pin while in the sleep state and is also o nly a transition state for the intel atom processor z5xx series. bclk may be stopped during the deep sleep state for additional platform level power savings. as an example, bclk stop/restart timings on appropriate chipset - based platforms with the ck540 clo ck chip are as follows: ? deep sleep entry : the system clock chip may stop/tristate bclk within 2 bclks of dpslp# assertion. it is permissible to leave bclk running during deep sleep. ? deep sleep exit : the system clock chip must start toggling bclk within 10 bclk periods within dpslp# de - assertion. to re - enter the sleep state, the dpslp# pin must be de - asserted. bclk can be re - started after dpslp# de - assertion as described above. a period of 15 microseconds (to allow for pll stabilization) must occur before th e processor can be considered to be in the sleep state. once in the sleep state, the slp# pin must be de - asserted to re - enter the stop - grant state. while in deep sleep state, the processor is incapable of responding to snoop transactions or latching interr upt signals. no transitions of signals are allowed on the fsb while the processor is in deep sleep state. when the processor is in deep sleep state, it will not respond to interrupts or snoop transactions. any transition on an input signal before the proce ssor has returned to stop - grant state will result in unpredictable behavior. 2.1.1.3.3 deeper sleep state the deeper sleep state is similar to the deep sleep state, but further reduces core voltage levels. one of the potential lower core voltage levels is achieved b y entering the base deeper sleep state. the deeper sleep state is entered through assertion of the dprstp# pin while in the deep sleep state. the following lower core voltage level is achieved by entering the intel enhanced deeper sleep state which is a su b - state of deeper sleep state. intel enhanced deeper sleep state is entered through assertion of the dprstp# pin while in the deep sleep only when the l2 cache has been completely shut down. refer to section 2.1.1.3.4 for further details on reducing the l2 cache and entering intel enhanced deeper sleep state. in response to entering deeper sleep, the processor drives the vid code corresponding to the deeper sleep core voltage on the vid[6:0] pins. exit from deeper sleep or intel enhanced deeper sleep state is initiated by dprstp# de- assertion when the core requests a package state other than c4 or the core requests a processor performance state other than the lowest operating point.
low power features datasheet 19 2.1.1.3.4 intel ? atom? processor z 5xx series c5 as mentioned previously in this document, each c - state has latency and transitory power costs associated with entering/exiting idle states. when the processor is interrupted, it must awake to service requests. if these requests occur at a hig h frequency, it is possible that more power will be consumed entering/exiting the states than will be saved. to alleviate this concern, the intel atom processor z5xx series implements a new state called ?intel atom processor z5xx series c5?. the intel atom processor z5xx series c5 is not exposed to software. the only way to enter the c5 state is using a hardware promotion of c4 (with the cache ways shrunk to zero). when the processor is in c4, the chipset assumes the processor has data in its cache. often, the processor has fully flushed its cache. to avoid waking up the processor to service snoops when there is no data in its caches, the processor will automatically promote c4 requests to c5 (when the cache is flushed). the chipset treats c5 as a non - snoopa ble state. therefore, all snoops will be completed from the i/o dma masters without waking up the processor . while similar, the intel atom processor z5xx series c5 differs from the core 2 duo t5000/t7000 c5 implementation. in the intel atom processor z5xx series c5, the v cc will not be powered below the retention of caches voltage ? there is no need to initialize the processor?s caches on a c5 exit, and c5 is not architecturally enumerated to software. this state is the same as the intel atom processor z5xx series c5 state. 2.1.1.4 c6 state c6 is a new low power state being introduced on the intel atom processor z5xx series. c6 behavior is the same as intel enhanced deeper sleep with the addition of an on - die sram. this memory saves the processor state allowing the processor to lower its main core voltage closer to 0 v. it is important to note that v cc cannot be lower while only 1 (one) thread is in c6 state. the processor threads can enter the c6 state by initiating a p_lvl6 i/o read to the p_blk or an mwait(c6) ins truction. to enter c6, the processor?s caches must be flushed. the primary method to enter c6 used by newer operating systems (that support mwait) will be through the mwait instruction. when the thread enters c6, it saves the processor state that is relev ant to the processor context in an on - die sram that resides on a separate power plane v ccp (i/o power supply). this allows the core v cc to be lowered to any arbitrary voltage including 0 v. the microcode performs the save and restore of the processor state on entry and exit from c6 respectively.
low power features 20 datasheet 2.1.1.4.1 intel ? deep power down technology state (package c6 state) when both threads have entered the c6 state and the l2 cache has been shrunk down to zero ways, the processor will enter the package deep power down techno logy state. to do so, the processor saves its architectural states in the on - die sram that resides in the v ccp domain. at this point, the core v cc will be dropped to the lowest core voltage (closer to 0.3 v). the processor is now in an extremely low - power state. while in this state, the processor does not need to be snooped as all the caches were flushed before entering the c6 state. the deep power down technology exit sequence is triggered by the chipset when it detects a break event. it de - asserts the dp rstp#, dpslp#, slp#, and stpclk# pins to return to c0. at dpslp# de - assertion, the core v cc ramps up to the lfm value and the processor starts up its internal plls. at slp# de - assertion the processor is reset and the architectural state is read back into t he threads from an on - die sram. refer to figure 3 and figure 4 for deep power down technology entry sequence and exit sequences. figure 3 . deep power down technology entry seque nce thread 1 tc0 thread 0 dpslp# assert dprstp# assert slp# assert stpclk# assert state save level 6 i/o read state save mwait c6 or level 6 i/o read mwait c6 or level 6 i/o read tc1 tc6 tc6 package c6 l2 shrink note: deep power down technology is referred to as c6 in the above figure. figure 4 . deep power down technology exit sequence dprst# deassert package c6 h/w reset ucode reset and state restore (tc1) tc0 dpsl# deassert slp# deassert stpclk# deassert tc0 ucode reset and state restore (tc0)
low power features datasheet 21 figure 5 shows the re lative exit latencies of the package sleep states discussed above. note: figure 5 uses pre - silicon estimates. silicon based data will be provided in a future revision of this document. figure 5 . exit latency ta ble latency (s) c0 (hfm ) c0 (lfm ) c1 both threads halted most clocks off c1e c1 plus frequency and vid at lfm c2 similar to c 1 but intel? sch blocks interrupts c4 c2 plus plls off ; vid = cache retention vcc some l 2 cache off c6 c2 plus plls off ; vid = c6 powerdown vcc l 2 cache off power (w) 0 0.1 1 10 100 0 tdp
low power features 22 datasheet 2.2 dynamic cache sizing dynamic cache sizing allows the processor to flush and disable a programmable number of l2 cache ways upon each deeper sleep entry under the following conditions: ? the c0 timer that tracks continuous residency in the normal package state has not expired. this timer is cleared during the first entry into deeper sleep to allow consecutive deeper sleep entries to shrink the l2 cache as needed. ? the fsb speed to processor core speed ratio is below the pred efined l2 shrink threshold. the number of l2 cache ways disabled upon each deeper sleep entry is configured in the bbl_cr_ctl3 msr. the c0 timer is referenced through the clock_core_cst_control_stt msr. the shrink threshold under which the l2 cache size i s reduced is configured in the pmg_cst_config_control msr. if the fsb speed to processor core speed ratio is above the predefined l2 shrink threshold, then l2 cache expansion will be requested. if the ratio is zero, then the ratio will not be taken into ac count for dynamic cache sizing decisions. upon stpclk# de - assertion, the core exiting intel enhanced deeper sleep state or c6 will expand the l2 cache to two ways and invalidate previously disabled cache ways. if the l2 cache reduction conditions stated a bove still exist when the core returns to c4 then package enters intel enhanced deeper sleep state or c6, then the l2 will be shrunk to zero again. if the core requests a processor performance state resulting in a higher ratio than the predefined l2 shrink threshold, the c0 timer expires, and then the whole l2 will be expanded upon the next interrupt event. in addition, the processor supports full shrink on l2 cache. when the mwait c6 instruction is executed with a hint=0x2 in ecx[3:0], the micro code will shrink all the active ways of the l2 cache in one step. this ensures that the package enters c6 immediately when it is in tc6 instead of iterating until the cache is reduced to zero. the operating system (os) is expected to use this hint when it wants to e nter the lowest power state and can tolerate the longer entry latency. l2 cache shrink prevention may be enabled as needed on occasion through an mwait(c4) sub - state field. if shrink prevention is enabled, the processor does not enter intel deeper sleep st ate or c6 since the l2 cache remains valid and in full size.
low power features datasheet 23 2.3 enhanced intel speedstep ? technology the processor features enhanced intel speedstep ? technology. the following are the key features of enhanced intel speedstep ? technology: ? multiple voltage and frequency operating points providing optimal performance at the lowest power . ? voltage and frequency selection is software controlled by writing to processor msrs: ? if the target frequency is higher than the current frequency, v cc is ramped up in steps by p lacing new values on the vid pins and the pll then locks to the new frequency. ? if the target frequency is lower than the current frequency, the pll locks to the new frequency and the v cc is changed through the vid pin mechanism. ? software transitions are ac cepted at any time. if a previous transition is in progress, the new transition is deferred until the previous transition completes. ? the processor controls voltage ramp rates internally to ensure glitch free transitions. ? low transition latency and a large number of transitions are possible per second: ? processor core (including l2 cache) is unavailable for up to 10 s during the frequency transition. ? the bus protocol (bnr# mechanism) is used to block snooping. ? improved intel thermal monitor mode: ? when the on - die thermal sensor indicates that the die temperature is too high, the processor can automatically perform a transition to a lower frequency and voltage specified in a software programmable msr. ? the processor waits for a fixed time period. if the die temp erature is down to acceptable levels, an up transition to the previous frequency and voltage point occurs. ? an interrupt is generated for the up and down intel thermal monitor transitions enabling better system level thermal management. ? enhanced thermal ma nagement features: ? digital thermal sensor and out of specification detection ? intel thermal monitor 1 (tm1) in addition to intel thermal monitor 2 (tm2) in case of unsuccessful tm2 transition.
low power features 24 datasheet 2.4 enhanced low - power states enhanced low - power states (c1e, c2e, a nd c4e ) optimize for power by forcibly reducing the performance state of the processor when it enters a package low - power state. instead of directly transitioning into the package low - power state, the enhanced package low - power state first reduces the perf ormance state of the processor by performing an enhanced intel speedstep technology transition down to the lowest operating point. upon receiving a break event from the package low - power state, control will be returned to software while an enhanced intel s peedstep technology transition up to the initial operating point occurs. the advantage of this feature is that it significantly reduces leakage while in the stop - grant and deeper sleep states. note: long - term reliability cannot be assured unless all the enhance d low - power sta t es are enabled. the processor implements two software interfaces for requesting enhanced package low - power states: mwait instruction extensions with sub - state hints and using bios by configuring ia32_misc_enables msr bits to automatically p romote package low - power states to enhanced package low - power states. caution: enhanced stop - grant and enhanced deeper sleep must be enabled using the bios for the processor to remain within specification. not complying with this guideline may affect the long - term reliability of the processor. enhanced intel speedstep ? technology transitions are multi - step processes that require clocked control. these transitions cannot occur when the processor is in the sleep or deep sleep package low - power states since processor clocks are not active in these states. enhanced deeper sleep is an exception to this rule when the hard c4e configuration is enabled in the ia32_misc_enables msr. this enhanced deeper sleep state configuration will lower core voltage to the deeper sleep le vel while in deeper sleep and, upon exit, will automatically transition to the lowest operating voltage and frequency to reduce snoop service latency. the transition to the lowest operating point or back to the original software requested point may not be instantaneous. furthermore, upon very frequent transitions between active and idle states, the transitions may lag behind the idle state entry resulting in the processor either executing for a longer time at the lowest operating point or running idle at a high operating point. observations and analyses show this behavior should not significantly impact total power savings or performance score while providing power benefits in most other cases.
low power features datasheet 25 2.5 fsb low power enhancements the processor incorporates fsb low p ower enhancements: ? bpri# control for address and control input buffers ? dynamic bus parking ? dynamic on die termination disabling ? low v ccp (i/o termination voltage) ? cmos front side bus the processor incorporates the dpwr# signal that controls the data bus in put buffers on the processor. the dpwr# signal disables the buffers when not used and activates them only when data bus activity occurs, resulting in significant power savings with no performance impact. bpri# control also allows the processor address and control input buffers to be turned off when the bpri# signal is inactive. dynamic bus parking allows a reciprocal power reduction in chipset address and control input buffers when the processor de - asserts its br0# pin. the on - die termination on the process or fsb buffers is disabled when the signals are driven low, resulting in additional power savings. the low i/o termination voltage is on a dedicated voltage plane independent of the core voltage, enabling low i/ o switching power at all times. 2.5.1 cmos front si de bus the process or has a hybrid signaling mode ? where data and address busses run in cmos mode and strobe signals operate in gtl mode. the reason to use gtl on strobe signals is to improve signal integrity. the implementation of a cmos bus offers substant ial power savings when compared with the traditional agtl+ bus.
low power features 26 datasheet 2.6 intel? burst performance technology (intel? bpt) the processor supports acpi performance states (p - states). the p - state referred to as p0 will be a request for intel ? burst performance techn ology ( intel? bpt). intel bpt opportunistically, and automatically, allows the processor to run faster than the marked frequency if the part is operating within the thermal design limits of the platform. intel bpt mode provides more performance on demand w ithout impacting or raising mid thermals. intel bpt can be enabled or disabled by bios .
electrical specifications datasheet 27 3 electrical specifications this chapter contains signal group descriptions, absolute maximum ratings, voltage identification, and power sequencing. the chapter als o includes dc specifications. 3.1 fsb, gtlref, and cmref the processor supports two kinds of signalling protocol: complementary metal oxide semiconductor (cmos), and advanced gunning transceiver logic (agtl+). the ?cmos fsb? terminology used in this document refers to a hybrid signaling mode, where data and address busses run in cmos mode and strobe signals operate in gtl mode. the reason to use gtl on strobe signals is to improve signal integrity. the termination voltage level for the processor cmos and agtl + signals is v ccp = 1.05 v (nominal). due to speed improvements to data and address bus, signal integrity and platform design methods have become more critical than with previous processor families. the cmos data and address busses require a reference vo ltage (cmref) that is used by the receivers to determine if a signal is a logical 0 or a logical 1. cmref is only applicable to data and address signals ? not to the sideband signals listed in table 5 . cmref must be generated on the system board. in cmos mode, there is no receiver - side termination to i/o voltage (v ccp ). the agtl+ inputs, including the sideband signals listed in table 5 , require a reference voltage (gtlref) that is used by the receivers to determine if a signal is a logical 0 or a logical 1. gtlref must be generated on the system board. termination resistors are provided on the processor silicon and are terminated to its i/o voltage (v ccp ). the appropriate chipset will also provide on - die te rmination, thus eliminating the need to terminate the bus on the system board for most agtl+ signals. the cmos bus depends on reflected wave switching and the agtl+ bus depends on incident wave switching. timing calculations for cmos and agtl+ signals are based on flight time as opposed to capacitive deratings. analog signal simulation of the fsb, including trace lengths, is highly recommended when designing a system. 3.2 power and ground pins for clean, on - chip power distribution, the processor will have a la rge number of v cc (power) and v ss (ground) inputs . all power pins must be connected to v cc power planes while all v ss p ins must be connected to system ground planes. use of multiple power and ground planes is recommended to reduce i*r drop . the processor v cc pins must be supplied by the voltage determined by the vid (voltage id) pins.
electrical specifications 28 datasheet 3.3 decoupling guidelines due to its large number of transistors and high internal clock speeds, the processor is capable of generating large average current swings between low an d full power states. this may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate. larger bulk storage, such as electrolytic capacitors, supplies current during longer lasting changes in current demand by the component ( such as , coming out of an idle condition ) . similarly, they act as storage well for current when entering an idle condition from a running condition. care must be taken in the board design to ensure that the voltage provided to the processor rem ains within the specifications listed in table 7 , table 7 , and table 7 . failure to do so can result in timing violations or reduced lifetime of the component. 3.3.1 v cc decoupling v cc regulator solutions need to provide bulk capacitance with a low effective series resistance (esr) and keep a low interconnect resistance from the regulator to the socket. bulk decoupling for the large current swings when the part is powering on or entering /exiting low - power states must be provided by the voltage regulator solution . 3.3.2 fsb agtl+ decoupling the processor integrates signal termination on the die. decoupling must also be provided by the system motherboard for proper agtl+ bus operation. 3.4 fsb cloc k (bclk[1:0]) and processor clocking bclk[1:0] directly controls the fsb interface speed as well as the core frequency of the processor. as in previous generation processors, the processor core frequency is a multiple of the bclk[1:0] frequency. the proces sor bus ratio multiplier will be set at its default ratio at manufacturing. the processor uses a differential clocking implementation. 3.5 voltage identification and power sequencing the processor uses seven voltage identification pins (vid[6:0]) to support a utomatic selection of power supply voltages. the vid pins for the processor are cmos outputs driven by the processor vid circuitry. table 3 specifies the voltage level corresponding to the state of vid[6:0]. a ?1? (one) in this re fers to a high - voltage level and a ?0? (zero) refers to low - voltage level. power source characteristics must be stable whenever the supply to the voltage regulator is stable.
electrical specifications datasheet 29 table 3 . voltage identification definition vid6 vid5 vi d4 vid3 vid2 vid1 vid0 v cc (v) 0 0 1 1 0 0 0 1.2000 0 0 1 1 0 0 1 1.1875 0 0 1 1 0 1 0 1.1750 0 0 1 1 0 1 1 1.1625 0 0 1 1 1 0 0 1.1500 0 0 1 1 1 0 1 1.1375 0 0 1 1 1 1 0 1.1250 0 0 1 1 1 1 1 1.1125 0 1 0 0 0 0 0 1.1000 0 1 0 0 0 0 1 1.0875 0 1 0 0 0 1 0 1.0750 0 1 0 0 0 1 1 1.0625 0 1 0 0 1 0 0 1.0500 0 1 0 0 1 0 1 1.0375 0 1 0 0 1 1 0 1.0250 0 1 0 0 1 1 1 1.0125 0 1 0 1 0 0 0 1.0000 0 1 0 1 0 0 1 0.9875 0 1 0 1 0 1 0 0.9750 0 1 0 1 0 1 1 0.9625 0 1 0 1 1 0 0 0.9500 0 1 0 1 1 0 1 0.93 75 0 1 0 1 1 1 0 0.9250 0 1 0 1 1 1 1 0.9125 0 1 1 0 0 0 0 0.9000 0 1 1 0 0 0 1 0.8875 0 1 1 0 0 1 0 0.8750 0 1 1 0 0 1 1 0.8625 0 1 1 0 1 0 0 0.8500 0 1 1 0 1 0 1 0.8375 0 1 1 0 1 1 0 0.8250 0 1 1 0 1 1 1 0.8125 0 1 1 1 0 0 0 0.8000 0 1 1 1 0 0 1 0.7875 0 1 1 1 0 1 0 0.7750 0 1 1 1 0 1 1 0.7625 0 1 1 1 1 0 0 0.7500 0 1 1 1 1 0 1 0.7375
electrical specifications 30 datasheet vid6 vid5 vi d4 vid3 vid2 vid1 vid0 v cc (v) 0 1 1 1 1 1 0 0.7250 0 1 1 1 1 1 1 0.7125 1 0 0 0 0 0 0 0.7000 1 0 0 0 0 0 1 0.6875 1 0 0 0 0 1 0 0.6750 1 0 0 0 0 1 1 0.6625 1 0 0 0 1 0 0 0.6500 1 0 0 0 1 0 1 0.6375 1 0 0 0 1 1 0 0.6250 1 0 0 0 1 1 1 0.6125 1 0 0 1 0 0 0 0.6000 1 0 0 1 0 0 1 0.5875 1 0 0 1 0 1 0 0.5750 1 0 0 1 0 1 1 0.5625 1 0 0 1 1 0 0 0.5500 1 0 0 1 1 0 1 0.5375 1 0 0 1 1 1 0 0.5250 1 0 0 1 1 1 1 0.5125 1 0 1 0 0 0 0 0. 5000 1 0 1 0 0 0 1 0.4875 1 0 1 0 0 1 0 0.4750 1 0 1 0 0 1 1 0.4625 1 0 1 0 1 0 0 0.4500 1 0 1 0 1 0 1 0.4375 1 0 1 0 1 1 0 0.4250 1 0 1 0 1 1 1 0.4125 1 0 1 1 0 0 0 0.4000 1 0 1 1 0 0 1 0.3875 1 0 1 1 0 1 0 0.3750 1 0 1 1 0 1 1 0.3625 1 0 1 1 1 0 0 0.3500 1 0 1 1 1 0 1 0.3375 1 0 1 1 1 1 0 0.3250 1 0 1 1 1 1 1 0.3125 1 1 0 0 0 0 0 0.3000
electrical specifications datasheet 31 3.6 catastrophic thermal protection the processor supports the thermtrip# signal for catastrophic thermal protection. an external thermal sensor should also b e used to protect the processor and the system against excessive temperatures. even with the activation of thermtrip#, which halts all processor internal clocks and activity, leakage current can be high enough such that the processor cannot be protected in all conditions without the removal of power to the processor. if the external thermal sensor detects a catastrophic processor temperature of 120c (maximum), or if the thermtrip# signal is asserted, the v cc supply to the processor must be turned off withi n 500 ms to prevent permanent silicon damage due to thermal runaway of the processor. thermtrip# functionality is not ensured if the pwrgood signal is not asserted. 3.7 reserved and unused pins rsvd[3:0] must be tied directly to v ccp (1.05 v) ? non c6 rail to en sure proper operation of the processor. all other rsvd signals can be left as no connect. connection of these pins to v cc , v ss , or to any other signal (including each other) can result in component malfunction or incompatibility with future processors. see section 4.2 for a pin listing of the processor and the location of all rsvd pins. for reliable operation, always connect unused inputs or bidirectional signals to an appropriate signal level. unused active low agtl+ inputs may be left as no connects if agtl+ te rmination is provided on the processor silicon. unused active high inputs should be connected through a resistor to ground (v ss ). unused outputs can be left unconnected. 3.8 fsb frequency select signals (bsel[2:0]) the bsel[2:0] signals are used to select th e frequency of the processor input clock (bclk[1:0]). these signals should be connected to the clock chip and the appropriate chipset on the platform. the bsel encoding for bclk[1:0] is shown in table 4 . table 4 . bsel[2:0] encoding for bclk frequency bsel[2] bsel[1] bsel[0] bclk frequency l l h 133 mhz h l h 100 mhz note: all other bus selections reserved. 3.9 fsb signal groups to simplify the following discussion, the fsb signals have been combined into groups by buffer type. agtl+ input signals have differential input buffers, which use gtlref as a reference level. in this document, the term ?agtl+ input? refers to the agtl+ input group as well as the agtl+ i/o group when receiving. similarly, ?agtl+ output? refer s to the agtl+ output group as well as the agtl+ i/o group when driving.
electrical specifications 32 datasheet i mplementation of a sour ce synchronous data bus determines the need to specify two sets of timing parameters. one set is for common clock signals which are dependent upon the rising edge of bclk0 (ads#, hit#, hitm#, and so on.) and the second set is for the source synchronous signals which are relative to their respective strobe lines (data and address) as well as the rising edge of bclk0. asynchronous signals are still present (a20m# , ignne#, and so on.) and can become active at any time during the clock cycle. table 5 identifies which signals are common clock, source synchronous, and asynchronous. table 5 . fsb pin groups signal group type signals1 agtl+ common clock input synchronous to bclk[1:0] bpri#, defer#, preq#4, reset#, rs[2:0]#, trdy#, dpwr# agtl+ common clock i/o synchronous to bclk[1:0] ads#, bnr#, bpm[3:0]#, br0#, dbsy#, drdy#, hit#, hitm#, lock#, prdy# cmos source synchr onous i/o synchronous to assoc. strobe signals associated strobe req[4:0]#, a[16:3]# adstb0# a[ 31:17]# adstb1# d[15:0]# dstbp0#, dstbn0# d[31:16]# dstbp1#, dstbn1# d[47:32]# dstbp2#, dstbn2# d[63:48]# dstbp3#, dstbn3# strobes always use agtl signaling ? data pins are cmos only. agtl+ strobes synchronous to bclk[1:0] adstb[1:0]#, dstbp[3:0]#, dstbn[3:0]# cmos input asynchronous dprstp#, dpslp#, ignne#, init#, lint0/intr, lint1/ nmi, pwrgood, smi#, slp#, stpclk# open drain output asynchronous ferr#, ther mtrip#, ierr# open drain i/o asynchronous prochot#3 cmos output asynchronous vid[6:0], bsel[2:0] cmos input synchronous to tck tck, tdi, tms, trst# open drain output synchronous to tck tdo fsb clock clock bclk[1:0] power/other comp[3:0], hfpll, cmr ef, gtlref , / dclk , /a dk , thermda, thermdc, v cc , v cca , v ccp , v cc_sense , v ss , v ss_sense , v ccfuse , v ccpc6 notes: 1. refer to chapter 4 for signal descriptions and termination requirements. 2. in processor systems where there is no debug port implemented on the system board, these signals are used to support a debug port interposer. in systems with the debug port implemented on the system board, these signals are no connects. 3. prochot# signal type is open drain output and cmos input. 4. on die termination differs from other agtl+ signals.
electrical specifications datasheet 33 3.10 cmos asynchronous signals cmos input signals are shown in table 5 . legacy outpu t ferr#, ierr# , and other non - agtl+ signals (thermtrip# and prochot#) use open drain output buffers. these signals do not have setup or hold time specifications in relation to bclk[1:0]. however, all of the cmos signals are required to be asserted for mor e than 5 bclks for the processor to recognize them. see section 3.12 for the dc specifications for the cmos signal groups. 3.11 maximum ratings table 6 specifies absolute maximum and minimum ratings. within functional operation limits, functionality and long - term reliability can be expected. at conditions outside functional operation condition limits, but within absolute maximum and minimum ratings, neither functionality nor long term reliabil ity can be expected. if a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits, but within the absolute maximum and minimum ratings, the device may be functional, but with its li fetime degraded depending on exposure to conditions exceeding the functional operation condition limits. at conditions exceeding absolute maximum and minimum ratings, neither functionality nor long term reliability can be expected. moreover, if a device is subjected to these conditions for any length of time then, when returned to conditions within the functional operating condition limits, it will either not function or its reliability will be severely degraded. although the processor contains protective circuitry to resist damage from static electric discharge, precautions should always be taken to avoid high static voltages or electric fields.
electrical specifications 34 datasheet table 6 . processor absolute maximum ratings symbol parameter min. max. unit notes 1 t st orage processor storage temperature - 40 85 c 2, 3, 4 v cc, vccp, vccpc6 any processor supply voltage with respect to v ss - 0.3 1.10 v 5 vcca pll power supply - 0.3 1.575 v vinagtl+ agtl+ buffer dc input voltage with respect to v ss - 0.1 1.10 v vinasynch_cmos cmos buffer dc input voltage with res pect to v ss - 0.1 1.10 v notes: 1. for functional operation, all processor electrical, signal quality, mechanical and thermal specifications must be satisfied. 2. storage temperature is applicable to storage conditions only. in this scenario, the processor must not r eceive a clock, and no lands can be connected to a voltage bias. storage within these limits will not affect the long term reliability of the device. for functional operation, refer to the processor case temperature specifications. 3. this rating applies to t he processor and does not include any tray or packaging. 4. failure to adhere to this specification can affect the long term reliability of the processor. 5. the v cc maximum supported by the process is 1.2 v but the parameter can change (burn in voltage is high er). 3.12 processor dc specifications the processor dc specifications in this section are defined at the processor core (pads) unless noted otherwise. see chapter 4 for the pin signal definitions and signal pin assignments. most of the signals on the fsb are in the agtl+ signal group. the dc specifications for these signals are listed in table 11 . dc specifications for the cmos group are listed in table 12. table 11 through table 13 list the dc specifications for the processor and are valid only while meeting specifications for junction temperature, clock frequen cy, and input voltages. the highest frequency mode (hfm) and lowest frequency mode (lfm) refer to the highest and lowest core operating frequencies supported on the processor. active mode load line specifications apply in all states except in the deep slee p and deeper sleep states. v cc,boot is the default voltage driven by the voltage regulator at power up in order to set the vid values. unless specified otherwise, all specifications for the processor are at t j = 90 c. care should be taken to read all note s associated with each parameter.
electrical specifica tions datasheet 35 table 7 . voltage and current specifications for the intel ? atom ? processor z560, z550, z540, z530, Z520, and z510 symbol parameter min. typ. max. unit notes 11 fsb frequency bclk frequency 100.00 ? 133.35 mhz v cc hfm v cc @ highest frequency mode (hfm) avid ? 1.10 v 1, 2, 10 v cc lfm v cc @ lowest frequency mode (lfm) 0. 8 ? avid v 1, 2 v cc , boot default v cc voltage for initial power up ? v cc lfm ? v 2, 6 v ccp agtl+ termination voltage 1.00 1.05 1.15 v 1 2, 14 v ccpc6 agtl+ termination voltage 1.00 1.05 1.15 v 12, 14 v cca pll supply voltage 1.425 1.5 1.575 v v ccdppwdn v cc @ deep power down technology (c6) 0.30 0.35 0.40 v 13 v ccdprslp v cc @ deeper sleep (c4) 0.75 ? 1.0 v 1, 2 v ccf fuse power supply 1 .00 1.05 1.10 v i ccdes i cc for processors recommended design target (estimated) for z540, z550 , z560 ? ? 4.0 a i ccdes i cc for processors recommended design target (estimated) for z530, Z520, z510 ? ? 3.5 a i cc processor number core frequency/voltage ? ? ? ? ? z560 hfm: 2.13 ghz lfm: 0.80 ghz ? ? 3.5 1.5 a 3, 4 z550 hfm: 2.0 ghz lfm: 0.80 ghz ? ? 3.5 1.5 a 3, 4 z540 hfm: 1.86 ghz lfm: 0.80 ghz ? ? 3.2 1.5 a 3, 4 z530 Z520 z510 hfm: 1.60 ghz lfm: 0.80 ghz hfm: 1.33 ghz lfm: 0.80 ghz hfm: 1. 10 ghz lfm: 0.60 ghz ? ? 2.50 1.25 2.50 1.25 2.50 1.25 a 3, 4 i ah, i sgnt i cc auto - halt and stop - grant hfm: 1.1 ? 2 . 0 ghz @ 1.10 volts lfm: 0.6 ? 0.8 ghz @ 0. 8 5 volts ? ? ? ? 2.0 1.3 a 3, 4 i dprslp i cc deeper sleep (c4) ? ? 0.2 a at 50 c 3, 4 di cc / dt v cc power supply current slew rate at processor package pin (estimated) ? ? 2.5 a/s 5, 7
electrical specifications 36 datasheet symbol parameter min. typ. max. unit notes 11 i cca i cc for v cca supply ? ? 130 ma i ccp + i ccp c6 i ccp + i ccp c6 before v cc stable ? ? 2.5 a 8 i ccp + i ccp c6 i ccp + i ccp c6 after v cc stable ? ? 1.5 a 9 notes: 1. each p rocessor is programmed with a maximum valid voltage identification value (vid), which is set at manufacturing and can not be altered. individual maximum vid values are calibrated during manufacturing such that two processors at the same frequency may have d ifferent settings within the vid range. note that this differs from the vid employed by the processor during a power management event (thermal monitor 2, enhanced intel speedstep technology, or enhanced halt state). typical avid range is 0.75 v to 1.1 v. 2. t he voltage specifications are assumed to be measured across v cc_sense and v ss_sense pins at the socket with a 100 - mhz bandwidth oscilloscope, 1.5 - pf maximum probe capacitance, and 1 - m ? minimum impedance. the maximum length of ground wire on the probe shoul d be less than 5 mm. ensure external noise from the system is not coupled in the scope probe. 3. specified at 90c t j . 4. specified at the nominal v cc . 5. measured at the bulk capacitors on the motherboard. 6. v cc ,boot tolerance is shown in figure 6 and figure 7 . 7. based on simulations and averaged over the duration of any change in current. specified by design/characterization at nominal v cc . not 100% tested. 8. this is a power - up peak current specification, which is ap plicable when v ccp is high and v cc_core is low. 9. this is a steady - state i cc current specification, which is applicable when both v ccp and v cc_core are high. 10. the v cc maximum supported by the process is 1.1 v but the parameter can change (burn in voltage is h igher). 11. unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical data. these specifications will be updated with characterized data from silicon measurements at a later date. 12. v ccp may be turned off durin g c6 power state ? v ccpc6 must always be powered on to 1.05 v - 5/+10% on all power states. 13. the v cc power supply needs to be set to 0.3v during c6 power state. 14. v ccp (voltage rail which is turned off in c6 , with split vtt enabled ) should ramp to 1.05 v while exiting c6 (deep power down technology state) at least 5s before v cc_core ramps to lfm vid. in addition, v ccpc6 rail should remain at 1.05 - 5 /+10 % during v ccp ramp coming out of c6.
electrical specifications datasheet 37 table 8 . voltage and current specifications for t he intel ? atom ? processor z500 symbol parameter min. typ. max. unit notes 11 fsb frequency bclk frequency ? 100.0 - ? mhz v cc hfm v cc @ highest frequency mode (hfm) avid ? 0.85 v 1, 2, 10 v cc lfm v cc @ lowest frequency mode (lfm) 0.75 ? avid v 1, 2 v cc,bo ot default v cc voltage for initial power up ? v cc lfm ? v 2, 6 v ccp agtl+ termination voltage 1.00 1.05 1.1 5 v 12, 14 v ccpc6 agtl+ termination voltage 1.00 1.05 1.15 v 12, 14 v cca pll supply voltage 1.425 1.5 1.575 v v ccdppwdn v cc at deep power down te chnology (c6) 0.30 0.35 0.40 v 13 v ccdprslp v cc at deeper sleep (c4) 0. 75 ? 0. 8 5 v 1, 2 i ccdes i cc for processors recommended design target (estimated) ? ? 2 .0 a i cc processor number core frequency/voltage ? ? ? ? ? z500 hfm: 0.8 ghz lfm: 0.6 ghz ? ? 0.8 0.6 a 3, 4 i ah , i sgnt hfm: 0.8 ghz @ 0.85 volts lfm: 0.6 ghz @ 0.75 volts ? ? 0.7 0.5 a 3, 4 i dprslp i cc deeper sleep (c4) ? ? 0.11 a at 50 c 3, 4 di cc /dt v cc power supply current slew rate at processor package pin (estimated) ? ? 2.5 a/s 5, 7 i cca i cc for v cca supply ? ? 130 ma i ccp + i ccp c6 i ccp + i ccp c6 before v cc stable ? ? 2.5 a 8 i ccp + i ccp c6 i ccp + i ccp c6 after v cc stable ? ? 1.5 a 9 notes: 1. each processor is programmed with a maximum valid voltage identification value (vid), which is set a t manufacturing and can not be altered. individual maximum vid values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the vid range. note that this differs from the vid employed by the pr ocessor during a power management event (thermal monitor 2, enhanced intel speedstep technology, or enhanced halt state). typical avid range is 0.75 v to 0.85 v. 2. the voltage specifications are assumed to be measured across v cc_sense and v ss_sense pins at s ocket with a 100 - mhz bandwidth oscilloscope, 1.5 - pf maximum probe capacitance, and 1 - m ? minimum impedance. the maximum length of ground wire on the probe should be less than 5 mm. ensure external noise from the system is not coupled in the scope probe. 3. sp ecified at 90c t j . 4. specified at the nominal v cc . 5. measured at the bulk capacitors on the motherboard.
electrical specifications 38 datasheet 6. v cc ,boot tolerance is shown in figure 6 and figure 7 . 7. based on simulations and averaged over the dur ation of any change in current. specified by design/characterization at nominal v cc . not 100% tested. 8. this is a power - up peak current specification, which is applicable when v ccp is high and v cc_core is low. 9. this is a steady - state i cc current specification , which is applicable when both v ccp and v cc_core are high. 10. the v cc maximum supported by the process is 1.1 v but the parameter can change (burn in voltage is higher). 11. unless otherwise noted, all specifications in this table are based on estimates and sim ulations or empirical data. these specifications will be updated with characterized data from silicon measurements at a later date. 12. v ccp may be turned off during c6 power state ?v ccpc6 must always be powered on to 1.05 v 5% on all power states. 13. the v cc pow er su pply needs to be set to 0.3 ? 0.4 v during c6 power state. 14. v ccp (voltage rail which is turned off in c6 , with split vtt enabled ) should ramp to 1.05 v while exiting c6 (deep power down technology state) at least 5 s before v cc_core ramps to lfm vid. in addition, v ccpc6 rail should remain at 1.05 ( - 5 /+10 % ) during v ccp ramp coming out of c6. table 9 . voltage and current specifications for the inte l ? atom ? processor z515 symbol parameter min. typ. max. unit notes 11 fsb frequency bclk frequency ? 100.0 ? mhz v cc bfm v @ burst frequency mode (bfm) avid ? 1.1 v 1, 2, 10 v cc hfm v @ highest frequency mode (hfm) avid ? 1.1 v 1, 2 , 10 v cc lfm v @ lowest freque ncy mode (lfm) 0.75 ? avid v 1, 2 v ccboot default v cc voltage for initial power up ? v cc lfm ? v 2, 6 v ccp agtl+ termination voltage 1.00 1.05 1.15 v 12, 14 v ccpc6 agtl+ termination voltage 1.00 1.05 1.15 v 12, 14 v cca pll supply voltage 1.425 1.5 1.57 5 v v ccdppwdn v @ deep power down technology (c6) 0.30 0.35 0.40 v 13 v ccprslp v @ deeper sleep (c4) 0. 75 ? 0. 8 5 v 1, 2 i ccdes i for processors recommended design target (estimated) ? ? 2 .0 a i cc processor number core frequency/voltage ? ? ? ? ? z5 15 bfm: 1.2 ghz hfm: 0.8 ghz lfm: 0.6 ghz ? ? 2.5 0.8 0.6 a 3, 4 , 15 i ah , i sgnt bfm: 1.2 ghz @ avid volts hfm: 0.8 ghz @ avid volts lfm: 0.6 ghz @ avid volts ? ? 0.9 0.7 0.5 a 3, 4 i dprslp i cc deeper sleep (c4) ? ? 0.11 a @ 50 c 3, 4
electrical specifications datasheet 39 symbol parameter min. typ. max. unit notes 11 di cc /dt v power sup ply current slew rate @ processor package pin (estimated) ? ? 2.5 a/s 5, 7 i cc a i cc a for v supply ? ? 130 ma i ccp + i ccp c6 i ccp + i ccp c6 before v stable ? ? 2.5 a 8 i ccp + i ccp c6 i ccp + i ccp c6 after v stable ? ? 1.5 a 9 notes: 1. each processor is programmed wit h a maximum valid voltage identification value (vid), which is set at manufacturing and can not be altered. individual maximum vid values are calibrated during manufacturing such that two processors at the same frequency may have different settings within t he vid range. note that this differs from the vid employed by the processor during a power management event (thermal monitor 2, enhanced intel speedstep technology, or enhanced halt state). typical avid range is 0.75 v to 0.85 v. 2. the voltage specifications are assumed to be measured across v cc_sense and v ss_sense pins at socket with a 100 - mhz bandwidth oscilloscope, 1.5 - pf maximum probe capacitance, and 1 - m ? minimum impedance. the maximum length of ground wire on the probe should be less than 5 mm. ensure e xternal noise from the system is not coupled in the scope probe. 3. specified at 90c t j . 4. specified at the nominal v cc . 5. measured at the bulk capacitors on the motherboard. 6. v cc ,boot tolerance is shown in figure 6 and figure 7 . 7. based on simulations and averaged over the duration of any change in current. specified by design/characterization at nominal v cc . not 100% tested. 8. this is a power - up peak current specification, which is applicable when v ccp is high a nd v cc_core is low. 9. this is a steady - state i cc current specification, which is applicable when both v ccp and v cc_core are high. 10. the v cc maximum supported by the process is 1.1 v but the parameter can change (burn in voltage is higher). 11. unless otherwise no ted, all specifications in this table are based on estimates and simulations or empirical data. these specifications will be updated with characterized data from silicon measurements at a later date. 12. v ccp and v ccpc6 must always be powered on to 1.05 v 5% on all power states. 13. the v cc power supply needs to be set to 0.3 to 0.4 v during c6 power state. 14. the intel atom processor z515 enables intel? burst performance technology (intel? bpt).
electrical specifications 40 datasheet figure 6 . active v cc and i cc loadline 10 mv = ripple slope = -5.7 mv/a at package vcc_sense, vss_sense pins. differential remote sense required. v cc (v) i cc (a) v cc, dc min[hfm][lfm] v cc min[hfm][lfm] v cc nom*1.5 % = vr st pt error 1/ v cc nom[hfm][lfm] v cc max[hfm][lfm] v cc, dc max[hfm][lfm] i cc max[hfm][lfm] note 1/ v cc set point error tolerance is per below: tolerance -------------------------------- 1.5% 11.5 mv v cc active mode vid code range ---------------------------------------- v cc > 0.7500 v (vid 0111100) v cc 0.7500 v (vid 0111100) 0
electrical specifications datasheet 41 figure 7 . deeper sleep v cc and i cc loadline 10 mv = ripple for psi# asserted slope = -5. 7 mv/a at package vcc_sense, vss_sense pins. differential remote sense required. v cc_core (v) i cc_core (a) v cc_core, dc min (deeper sleep) v cc_core min (deeper sleep) v cc_core tolerance = vr st pt error 1/ v cc_core nom (deeper sleep) v cc_core max (deeper sleep) v cc_core, dc max (deeper sleep) i cc_core max (deeper sleep) note 1/ deeper sleep vcc_core set point error tolerance is per below: tolerance ? psi# ripple -------------------------------- [(vid*1 .5%) ? 3 mv] (11.5 mv) ? 3 mv] (25 mv) ? 3 mv] v cc_core vid voltage range ---------------------------------------- v cc_core > 0.7500 v 0.7500 v v cc_core 0.5000 v 0.5000 v < v cc_core 0.4125 v 0
electrical specifications 42 datasheet table 10 . fsb differential bclk specifications symbol parameter min. typ. max. unit figure notes 1 v ih inpu t high voltage ? ? 1.15 v 7, 8 v il input low voltage ? ? - 0.3 v 7, 8 v cross crossing voltage 0.3 ? 0.55 v 2, 7, 9 ?v cross range of crossing points ? ? 140 mv 2, 7, 5 v swing differential output swing 300 ? ? mv 6 i li input leakage current - 5 ? +5 a 3 cpad pad capacitance 1.2 1.45 2.0 pf 4 notes: 1. unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. crossing voltage is defined as absolute voltage where rising edge of bclk0 is equal to the falling edge of bclk1. 3. for vin between 0 v and v i h . 4. cpad includes die capacitance only. no package parasitics are included. 5. ?v cross is defined as the total variation of all crossing voltages as defined in note 2. 6. measurement taken from differential waveform. 7. measurement taken from single - ended waveform. 8. ?steady state? voltage, not including overshoots or undershoots. 9. only appli es to the differential rising edge (bclk0 rising and bclk1 falling).
electrical specifications datasheet 43 table 11 . agtl+/cmos signal group dc specifications symbol parameter min. typ. max. unit notes 1 v ccp i/o voltage 1.00 1.05 1.10 v 12 v ccpc6 i/o voltage for c6 1.00 1.05 1.10 v 12 gtlref gtl reference voltage ? 2/3 v ccp ? v 6 cmref cmos reference voltage ? 1/2 v ccp ? v 6 r comp compensation resistor 27.23 27.5 27.78 ? 10 r odt termination resistor ? 55 ? ? 11 v ih input high voltage gtlref+0.10 or cmref+0.10 v ccp v ccp +0.10 v 3, 6 v il input low voltage - 0.10 0 gtlref ? 0.10 or cmref ? 0.10 v 2, 4 v oh output high voltage v ccp ? 0.10 v ccp v ccp v 6 r tt termination resistanc e 46 [ss] 46 [cc] 55 61 [ss] 64 [cc] ? 7, 13 r on (gtl mode) gtl buffer on resistance 21 25 29 ? 5 r on (cmos mode) cmos buffer on resistance 42 [ss] 42 [cc] 50 55 [ss] 58 [cc] ? 5, 13 i li input leakage current ? ? 100 a 8 cpad pad capacitance 1.8 2. 1 2.75 pf 9 notes: 1. unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. v il is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value. 3. v ih is defined as the minimum volta ge level at a receiving agent that will be interpreted as a logical high value. 4. v ih and v oh may experience excursions above v ccp . however, input signal drivers must comply with the signal quality specifications. 5. this is the pull - down driver resistance. mea sured at 0.31*v ccp . r on (minimum) = 0.4*r tt , r on (typical) = 0.455*r tt , r on (maximum) = 0.51*r tt . r tt typical value of 55 ? is used for r on typical/minimum/maximum calculations. 6. gtlref and cmref should be generated from v ccp with a 1% tolerance resistor di vider. the v ccp referred to in these specifications is the instantaneous v ccp . 7. r tt is the on - die termination resistance measured at v ol of the agtl+ output driver. measured at 0.31*v ccp . r tt is connected to v ccp on die. 8. specified with on die r tt and r on a re turned off. vin between 0 and v ccp . 9. cpad includes die capacitance only. no package parasitics are included. 10. there is an external resistor on the comp0 and comp2 pins. 11. on die termination resistance, measured at 0.33*v ccp . 12. v ccp =v ccp c6 during normal operat ion. when in c6 state, v ccp =0 v while v ccp c6=1.05 v. 13. ss: source synchronous pins such as quad - pumped data bus and double - pumped address bus which require a clock strobe. cc: common clock pins.
electrical specifications 44 datasheet table 12 . legacy cmos signal group dc s pecifications symbol parameter min. typ. max. unit notes 1 v ccp i/o voltage 1.00 1.05 1.10 v 8 v ccp c6 i/o voltage for c6 1.00 1.05 1.10 v 8 v ih input high voltage 0.7*v ccp v ccp vccp+0.1 v 2 v il input low voltage cmos - 0.10 0.00 0.3*v ccp v 2 v oh output high voltage 0.9*v ccp v ccp v ccp +0.1 v 2 v ol output low voltage - 0.10 0 0.1*v ccp v 2 i oh output high current 1.5 ? 4.1 ma 4 i ol output low current 1.5 ? 4.1 ma 3 i l i input leakage current ? ? 100 a 5 cpad1 pad capacitance 1.6 2.1 2.55 pf 6 cpad2 p ad capacitance for cmos input 0.95 1.2 1.45 7 notes: 1. unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. the v ccp referred to in these specifications refers to instantaneous v ccp . 3. measured at 0.1*v ccp . 4. measured at 0.9* v ccp . 5. for vin between 0v and v ccp . measured when the driver is tri - stated. 6. cpad1 includes die capacitance only for dprstp#, dpslp#, pwrgood. no package parasitics are included. 7. cpad2 includes die capacitance for all other cmos input signals. no package pa rasitics are included. 8. v ccp c6 = v ccp during normal operation and a specific tolerance may be added for this later. table 13 . open drain signal group dc specifications symbol parameter min. typ. max. unit notes 1 v oh output high volt age v ccp - ? 5% v ccp v ccp +5% v 3 v ol output low voltage 0 ? 0.20 v i ol output low current 16 ? 50 ma 2 i lo output leakage current ? ? 200 a 4 cpad pad capacitance 1.9 2.2 2.45 pf 5 notes: 1. unless otherwise noted, all specifications in this table apply to al l processor frequencies. 2. measured at 0.2 v. 3. v oh is determined by value of the external pull - up resistor to v ccp . 4. for vin between 0 v and v oh . 5. cpad includes die capacitance only. no package parasitics are included.
electr ical specifications datasheet 45 3.13 agtl+ fsb specifications termination resi stors are not required for most agtl+ signals, as these are integrated into the processor silicon. valid high and low levels are determined by the input buffers which compare a signal?s voltage with a reference voltage called gtlref (known as v ref in previ ous documentation). table 11 lists the gtlref and cmref specifications. the agtl+ and cmos reference voltages (gtlref and cmref) should be generated on the system board using high precision voltage divider circuits. it is importan t that the system board impedance is held to the specified tolerance, and that the intrinsic trace capacitance for the agtl+ signal group traces is known and well - controlled.
electrical specifications 46 datasheet this page intentionally left blank.
package mechanical specifications and pin information datasheet 47 4 package mechanical specifications and p in information this chapte r describes the package specifications, pinout assignments, and signal descriptions. 4.1 package mechanical specifications the processor will be available in 512 kb, 441 pins in fcbga8 package. the package dimensions are shown in figure 8 . 4.1.1 processor package weight the intel atom processor z5xx series package weight is 0.475 g.
package mechanical specifications and pin information 48 datasheet figure 8 . package mechanical drawing
package mechanical specifications and pin information datasheet 49 4.2 processor pinout assignment figure 9 and figure 10 are graphic representations of the processor pinout assignments. table 14 lists the pinout by signal name. figure 9 . pinout diagram (top vie w, left side) aj ah ag af ae ad ac ab aa y w v u t 1 vss /nctf d[61]# dstbn[3]# d[51]# vss thermtrip# 1 2 vss /nctf d[60]# d[59]# d[62]# vcc vid[6] 2 3 vss /nctf d[54]# vss vss vss vss vss 3 4 vss /nctf d[53]# d[57]# d [63]# dstbp[3]# d[58]# thrmdc 4 5 d[48]# d[52]# vss d[49]# dinv[3]# vss thrmda 5 6 d[50]# vss d[56]# d[55]# vss vss vcc 6 7 d[45]# d[40]# d[33]# vccp vss vss vss 7 8 d[46]# vss d[32]# vss vccp vcc vcc 8 9 d[36]# d[35] # vss vccp vss vss vss 9 10 d[47]# vss d[37]# vss vccp vcc vcc 10 11 dstbn[2] # dstbp[2] # vss vccp vss vss vss 11 12 d[44]# vss dinv[2]# vss vccp vcc vcc 12 13 d[42]# d[39]# comp[1] vccp vss vss vss 13 14 d[43]# vss c omp[0] vss vccp vcc vcc 14 15 d[34]# d[41]# rsvd vccp vss vss vss 15 16 d[38]# vss rsvd vss vccp vcc vcc 16 17 d[27]# rsvd rsvd vccp vss vss vss 17 18 d[30]# vss d[26]# vss vccp vcc vcc 18 19 d[24]# d[31]# d[28]# v ccp vss vss vss 19 20 d[18]# vss d[19]# vss vccp vcc vcc 20 21 dstbp[1]# dstbn[1] # vss vccp vss vss vss 21 22 d[20]# vss dinv[1]# vss vccp vcc vcc 22 23 d[23]# d[25]# vss vccp vss vss vss 23 24 d[29]# vss d[16]# d[17] # vss vcc vcc 24 25 d[22]# d[21]# vss d[14]# vss vss vss 25 26 gtlref vss cmref d[15]# d[6]# vccp vccp 26 27 d[1]# d[11]# d[12]# vss d[0]# test3 vss 27 28 vss /nctf d[13]# dinv[0]# d[9]# dstbn[0]# drdy# bsel[2] 28 29 vs s /nctf d[5]# vss vss vss vss vss 29 30 vss /nctf d[4]# d[3]# dstbp[0]# d[8]# test4 30 31 vss /nctf d[10]# d[7]# d[2]# dpwr# test2 31 aj ah ag af ae ad ac ab aa y w v u t
package mechanical specifications and pin i nformation 50 datasheet figure 10 . pinout diagr am (top view, right side) r p n m l k j h g f e d c b a 1 tms tdo stpclk# ierr# bpm[0]# vss /nctf 2 vid[5] tdi tck slp# dprstp# bpm[1]# vss /nct f 2 3 vss vss vss vss vss bpm[3]# vss /nctf 3 4 vid[1] vid[2] vid[4] trst# pwrgood prdy# a[29]# vss /nctf 4 5 vid[0] reset# vid[3] prochot# bpm[2]# a[19]# a[17]# 5 6 vcc vcc vss vss dpslp# rsvd vss a[22]# 6 7 vss vss vss vccpc6 preq# rsvd a[26]# 7 8 vcc vcc vcc vccpc6 vss rsvd vss a[ 28]# 8 9 vss vss vss vccpc6 vss rsvd a[21]# 9 10 vcc vcc vcc vccp vss rsvd vss a[25]# 10 11 vss vss vss vccp vss adstb[1]# a[31]# 11 12 vcc vcc vcc vccp vss a[20]# vss a[18]# 12 13 vss vss vss vccp vss a[27]# a[2 3]# 13 14 vcc vcc vcc vccp vss a[24]# vss a[30]# 14 15 vss vss vss vccp comp[3] a[12]# a[16]# 15 16 vcc vcc vcc vccp vss comp[2] vss a[10]# 16 17 vss vss vss vccp vss a[15]# a[7]# 17 18 vcc vcc vcc vccp vss a[11] # vss a[8]# 18 19 vss vss vss vccp vss adstb[0]# a[13]# 19 20 vcc vcc vcc vccp vss req[2]# vss a[14]# 20 21 vss vss vss vccp vss a[5]# req[4]# 21 22 vcc vcc vcc vccp vss a[3]# vss a[4]# 22 23 vss vss vss vccp vss req[1]# a[9]# 23 24 vcc vcc vcc vss bpri# a[6]# vss req[3]# 24 25 vss vss vss bnr# trdy# lock# req[0]# 25 26 vccp vccp vccp smi# rsvd rs[2]# ads# rsvd 26 27 vss vccp c6 rsvd ignne# vss rs[0]# defer# 27 28 bclk[1] v ss lint1 ferr# rsvd rs[1]# br0# vss /nctf 28 29 bclk[0] vss rsvd vss hitm# dbsy# vss /nctf 29 30 bsel[0] vcca rsvd rsvd a20m# hit# vss /nct f 30 31 test1 bsel[1] vss lint0 init# vss /nctf 31 r p n m l k j h g f e d c b a
package mechanical specifications and pin information datasheet 51 table 14 . pinout arranged b y signal name signal name ball # a[3]# e22 a[4]# a22 a[5]# d21 a[6]# e24 a[7]# b17 a[8]# a18 a[9]# b23 a[10]# a16 a[11]# e18 a[12] # d15 a[13]# b19 a[14]# a20 a[15]# d17 a[16]# b15 a[17]# b5 a[18]# a12 a[19]# d5 a[20]# e12 a[21]# b9 a[22]# a6 a[23]# b13 a[24]# e14 a[25]# a10 a[26]# b7 a[27]# d13 a[28]# a8 a[29]# c4 a[30]# a14 a[31]# b11 signal name ball # a20m# g30 ads# c26 adstb[0]# d19 adstb[1]# d11 bclk[0] p29 bclk[1] r28 b nr# h25 bpm[0]# f1 bpm[1]# e2 bpm[2]# f5 bpm[3]# d3 bpri# g24 br0# c28 rsvd g26 bsel[0] r30 bsel[1] m31 bsel[2] u28 cmref[1] ae26 comp[0] ae14 comp[1] ad13 comp[2] e16 comp[3] f15 d[0]# y27 d[1]# ah27 d[2]# y31 d[3]# ac30 d[4]# ae30 d[ 5]# af29 d[6]# aa26 signal name ball # d[7]# ab31 d[8]# w30 d[9]# ac28 d[10]# ad31 d[11]# af27 d[12]# ad27 d[13]# ag28 d[14]# ab25 d[15]# ac26 d[16]# ae24 d[17]# ac24 d[18]# aj20 d[19]# ae20 d[20]# aj22 d[21]# af25 d[22]# ah25 d[23]# ah23 d[24]# ah19 d[25 ]# af23 d[26]# ae18 d[27]# ah17 d[28]# ad19 d[29]# aj24 d[30]# aj18 d[31]# af19 d[32]# ae8 d[33]# ad7 d[34]# ah15 d[35]# af9
package mechanical specifications and pin information 52 datasheet signal name ball # d[36]# ah9 d[37]# ae10 d[38]# aj16 d[39]# af13 d[40]# af7 d[41]# af15 d[42]# ah13 d[43]# aj14 d[44]# aj12 d[45] # ah7 d[46]# aj8 d[47]# aj10 d[48]# ah5 d[49]# ab5 d[50]# aj6 d[51]# y1 d[52]# af5 d[53]# ag4 d[54]# af3 d[55]# ac6 d[56]# ae6 d[57]# ae4 d[58]# w4 d[59]# ac2 d[60]# ae2 d[61]# ad1 d[62]# aa2 d[63]# ac4 dbsy# d29 defer# b27 dinv[0]# ae 28 signal name ball # dinv[1]# ae22 dinv[2]# ae12 dinv[3]# y5 dprstp# g2 dpslp# g6 dpwr# v31 drdy# w28 dstbn[0]# aa28 dstbn[1]# af21 dstbn[2]# ah11 dstbn[3]# ab1 dstbp[0]# aa30 dstbp[1]# ah21 dstbp[2]# af11 dstbp[3]# aa4 ferr# j28 rsvd g28 gtlref aj26 hit# e30 hitm# f29 ierr# h1 ignne# h27 init# f31 lint0 h31 lint1 l28 lock# d25 prdy# e4 preq# f7 prochot# h5 pwrgood g4 req[0]# b25 signal name ball # req[1]# d23 req[2]# e20 req[3]# a24 req[4]# b21 reset# m5 rs[0]# d27 rs[1]# e28 rs[2]# e26 rsvd k29 rs vd d 9 rs vd d 7 rs vd e8 rs vd e10 rs vd l30 rs vd j30 rs vd e6 rs vd ae16 rs vd af17 rs vd ad15 rs vd ad17 rs vd a26 rs vd k27 slp# j2 smi# j26 stpclk# k1 tck l2 tdi n2 tdo m1 test1 p31 test2 t31 test3 v27
package mechanical specifications and pin information datasheet 53 signal name ball # test4 u30 thermtrip# t1 thrmda t5 thrmdc u4 tms p1 trdy# f25 trst# j4 vcc l8 vcc l10 vcc l12 vcc l14 vcc l16 vcc l18 vcc l20 vcc l22 vcc l24 vcc n6 vcc n8 vcc n10 vcc n12 vcc n14 vcc n16 vcc n18 vcc n20 vcc n22 vcc n24 vcc r6 vcc r8 vcc r10 vcc r12 vcc r14 signal name ball # vcc r16 vcc r18 vcc r20 vcc r22 vcc r24 vcc u6 vcc u8 vcc u10 vcc u12 vcc u14 vcc u16 vcc u18 vcc u20 vcc u22 vcc u24 vcc w8 vcc w10 vcc w12 vcc w14 vcc w16 vcc w18 vcc w20 vcc w22 vcc w24 vcca n30 vccp aa8 vccp aa10 vccp aa12 vccp aa16 vccp aa18 vccp aa20 signal name ball # vccp aa22 vccp ab7 vccp ab9 vccp ab11 vccp ab13 vccp ab15 vccp ab17 vccp ab19 vccp ab21 vccp ab23 vccp h11 vccp h13 vccp h15 vccp h17 vccp h19 vccp h21 vccp h23 vccp j10 vccp j12 vccp j14 vccp j18 vccp j20 vccp j22 vccp l26 vccp n26 vccp r26 vccp u26 vccp w26 vccp aa14 vccp j16 vccpc6 h7
package mechanical specifications and pin information 54 datasheet signal name ball # vccpc6 h9 vccpc6 j8 vccp c6 m27 vcc_ sense w2 vid[0] p5 vid[1] r4 vid[2] n4 vid[3] k5 vid[4] l4 vid[5] r2 vid[6] u2 vss k31 vss /nctf a4 vss /nctf a28 vss aa6 vs s aa24 vss ab3 vss ab27 vss ab29 vss ac8 vss ac10 vss ac12 vss ac14 vss ac16 vss ac18 vss ac20 vss ac22 vss ad3 vss ad5 vss ad9 vss ad11 signal name ball # vss ad21 vss ad23 vss ad25 vss ad29 vss /nctf af1 vss /nctf af31 vss /nctf ag2 vss ag6 vss ag8 vs s ag10 vss ag12 vss ag14 vss ag16 vss ag18 vss ag20 vss ag22 vss ag24 vss ag26 vss /nctf ag30 vss /nctf ah3 vss /nctf ah29 vss /nctf aj4 vss /nctf aj28 vss /nctf b3 vss /nctf b29 vss /nctf c2 vss c6 vss c8 vss c10 vss c12 vss c14 signal name ball # vss c16 vss c18 vss c20 vss c22 vss c24 vss /nctf c30 vss /nctf d1 vss /nctf d31 vss f3 vss f9 vss f11 vss f13 vss f17 vss f19 vss f21 vss f23 vss f27 vss g8 vss g10 vss g12 vss g14 vss g16 vss g18 vss g20 vss g22 vss h3 vss h29 vss j6 vss j24 vss k3 vss k7
package mechanical speci fications and pin information datasheet 55 signal name ball # vss k9 vss k11 vss k13 vss k15 vss k17 vss k19 vss k21 vss k23 vss k25 vss l6 vss m3 vss m7 vss m9 vss m11 vss m13 vss m15 vss m17 vss m19 vss m21 vss m23 vss m25 vss m29 vss n28 vss p3 vss p7 vss p9 signal name ball # vss p11 vss p13 vss p15 vss p17 vss p19 vss p21 vss p23 vss p25 vss p27 vss t3 vss t7 vss t9 vss t11 vss t13 vss t15 vss t17 vss t19 vss t21 vss t23 vss t25 vss t27 vss t29 vss v3 vss v5 vss v7 vss v9 signal name ball # vss v11 vss v13 vss v15 vss v17 vss v 19 vss v21 vss v23 vss v25 vss v29 vss w6 vss y3 vss y7 vss y9 vss y11 vss y13 vss y15 vss y17 vss y19 vss y21 vss y23 vss y25 vss y29 vss _ sense v1
56 datasheet 4.3 signal description table 15 . signal description signal name t ype description a[31:3]# i/o a[31:3]# (address) defines a 2 32 - byte physical memory address space. in subphase 1 (one) of the address phase, these pins transmit the address of a transaction. in sub - phase 2, these pins transmit transaction type information. these signals must connect the appropriate pins of both agents on the processor fsb. a[31:3]# are source synchronous signals and are latched into the receiving buffers by adstb[1:0]#. address signals are used as straps which are sampled before reset# is d e - asserted. a20m# i if a20m# (address - 20 mask) is asserted, the processor masks physical address bit 20 (a20#) before looking up a line in any internal cache and before driving a read/write transaction on the bus. asserting a20m# emulates the 8086 process or's address wrap - around at the 1 - mb boundary. assertion of a20m# is only supported in real mode. a20m# is an asynchronous signal. however, to ensure recognition of this signal following an input/output write instruction, it must be valid along with the tr dy# assertion of the corresponding input/output write bus transaction. ads# i/o ads# (address strobe) is asserted to indicate the validity of the transaction address on the a[31:3]# and req[4:0]# pins. all bus agents observe the ads# activation to begin p arity checking, protocol checking, address decode, internal loop, or deferred reply id match operations associated with the new transaction. adstb[1:0]# i/o address strobes are used to latch a[31:3]# and req[4:0]# on their rising and falling edges. strobe s are associated with signals as shown below. signals associated strobe req[4:0]#, a[16:3]# adstb[0]# a[31:17]# adstb[1]# bclk[1:0] i the differential pair bclk (bus clock) determines the fsb frequency. all fsb agents must receive these signals to drive t heir outputs and latch their inputs. all external timing parameters are specified with respect to the rising edge of bclk0 crossing vcross. bnr# i/o bnr# (block next request) is used to assert a bus stall by any bus agent who is unable to accept new bus transactions. during a bus stall, the current bus owner cannot issue any new transactions.
package mechanical specifications and pin information datasheet 57 signal name t ype description bpm[0]# o bpm[3:0]# (breakpoint monitor) are breakpoint and performance monitor signals. they are outputs from the processor which indicate the status of breakpoint s and programmable counters used for monitoring processor performance. bpm[3:0]# should connect the appropriate pins of all fsb agents. this includes debug or performance monitoring tools. bpm[1]# i/o bpm[2]# o bpm[3]# i/o bpri# i bpri# (bus priori ty request) is used to arbitrate for ownership of the fsb. it must connect the appropriate pins of both fsb agents. observing bpri# active (as asserted by the priority agent) causes the other agent to stop issuing new requests, unless such requests are par t of an ongoing locked operation. the priority agent keeps bpri# asserted until all of its requests are completed then releases the bus by de - asserting bpri#. br0# i/o br0# is used by the processor to request the bus. the arbitration is done between the p rocessor (symmetric agent) and intel? sch (high priority agent). bsel[2:0] o bsel[2:0] (bus select) are used to select the processor input clock frequency. table 4 defines the possible combinations of the signals and the frequenc y associated with each combination. the required frequency is determined by the processor, chipset and clock synthesizer. all agents must operate at the same frequency. the processor operates at 400 - mhz or 533 - mhz system bus frequency100 - mhz or 133 - mhz bcl k frequency, respectively). comp[3:0] pwr comp[3:0] must be terminated on the system board using precision (1% tolerance) resistors. d[63:0]# i/o d[63:0]# (data) are the data signals. these signals provide a 64- bit data path between the fsb agents, and must connect the appropriate pins on both agents. the data driver asserts drdy# to indicate a valid data transfer. d[63:0]# are quad - pumped signals and will thus be driven four times in a common clock period. d[63:0]# are latched off the falling edge of bo th dstbp[3:0]# and dstbn[3:0]#. each group of 16 data signals correspond to a pair of one dstbp# and one dstbn#. the following table shows the grouping of data signals to data strobes and dinv#. quad - pumped signal groups data group dstbn#/dstbp# dinv# d[15 :0]# 0 0 d[31:16]# 1 1 d[47:32]# 2 2 d[63:48]# 3 3 furthermore, the dinv# pins determine the polarity of the data signals. each group of 16 data signals corresponds to one dinv# signal. when the dinv# signal is active, the corresponding data group is inver ted and therefore sampled active high.
58 datasheet signal name t ype description dbsy# i/o dbsy# (data bus busy) is asserted by the agent responsible for driving data on the fsb to indicate that the data bus is in use. the data bus is released after dbsy# is de - asserted. this signal must connect the appropriate pins on both fsb agents. defer# i defer# is asserted by an agent to indicate that a transaction cannot be guaranteed in - order completion. assertion of defer# is normally the responsibility of the addressed memory or input/output agent. thi s signal must connect the appropriate pins of both fsb agents. dinv[3:0]# i dinv[3:0]# (data bus inversion) are source synchronous and indicates the polarity of the d[63:0]# signals. the dinv[3:0]# signals are activated when the data on the data bus is in verted. the bus agent will invert the data bus signals if more than half the bits, within the covered group, would change level in the next cycle. dinv[3:0]# assignment to data bus signals is shown below. bus signal data bus signals dinv[3]# d[63:48]# dinv [2]# d[47:32]# dinv[1]# d[31:16]# dinv[0]# d[15:0]# dprstp# i dprstp# when asserted on the platform causes the processor to transition from the deep sleep state to the deeper sleep state. in order to return to the deep sleep state, dprstp# must be de - ass erted. dprstp# is driven by the sch chipset. dpslp# i dpslp# when asserted on the platform causes the processor to transition from the sleep state to the deep sleep state. in order to return to the sleep state, dpslp# must be de - asserted. dpslp# is driven by the sch chipset. dpwr# i dpwr# is a control signal from the intel? sch used to reduce power on the processor data bus input buffers. drdy# i/o drdy# (data ready) is asserted by the data driver on each data transfer, indicating valid data on the data bus. in a multi - common clock data transfer, drdy# may be de - asserted to insert idle clocks. this signal must connect the appropriate pins of both fsb agents. dstbn[3:0]# i/o data strobe used to latch in d[63:0]#. signals associated strobe d[15:0]# dinv[0] #, dstbn[0]# d[31:16]# dinv[1]#, dstbn[1]# d[47:32]# dinv[2]#, dstbn[2]# d[63:48]# dinv[3]#, dstbn[3]# dstbp[3:0]# i/o data strobe used to latch in d[63:0]#. signals associated strobe d[15:0]# dinv[0]#, dstbp[0]# d[31:16]# dinv[1]#, dstbp[1]# d[47:32]# di nv[2]#, dstbp[2]# d[63:48]# dinv[3]#, dstbp[3]#
package mechanical specifications and pin information datasheet 59 signal name t ype description ferr#/pbe# o ferr# (floating - point error) pbe# (pending break event) is a multiplexed signal and its meaning is qualified with stpclk#. when stpclk# is not asserted, ferr#/pbe# indicates a floating point whe n the processor detects an unmasked floating - point error. ferr# is similar to the error# signal on the intel 387 coprocessor, and is included for compatibility with systems using msdos* - type floating - point error reporting. when stpclk# is asserted, an ass ertion of ferr#/pbe# indicates that the processor has a pending break event waiting for service. the assertion of ferr#/pbe# indicates that the processor should be returned to the normal state. when ferr#/pbe# is asserted, indicating a break event, it will remain asserted until stpclk# is de - asserted. assertion of preq# when stpclk# is active will also cause an ferr# break event. for additional information on the pending break event functionality, including identification of support of the feature and enabl e/disable information, refer to volume 3 of the intel ? 64 and ia - 32 architectures software developer's manuals and the intel ? processor identification and cpuid instruction application note . cmref pwr cmref determines the signal reference level for cmos input pins. cmref should be set at 1/2 v ccp . cmref is used by the cmos receivers to determine if a signal is a logical 0 or logical 1. if not using cmos, then all cmref and gtlref should be provided with 2/3 v ccp . gtlref pwr gtlref determines the signal reference level for agtl+ input pins. gtlref should be set at 2/3 v ccp . gtlref is used by the agtl+ receivers to determine if a signal is a logical 0 or logical hit# hitm# i/o hit# (snoop hit) and hitm# (hit modified) convey transaction snoop operation r esults. either fsb agent may assert both hit# and hitm# together to indicate that it requires a snoop stall, which can be continued by reasserting hit# and hitm# together. ierr# o ierr# (internal error) is asserted by a processor as the result of an inter nal error. assertion of ierr# is usually accompanied by a shutdown transaction on the fsb. this transaction may optionally be converted to an external error signal (for example, nmi) by system core logic. the processor will keep ierr# asserted until the as sertion of reset# or init#. ignne# i ignne# (ignore numeric error) is asserted to force the processor to ignore a numeric error and continue to execute non - control floating - point instructions. if ignne# is de - asserted, the processor generates an exceptio n on a non - control floating - point instruction if a previous floating - point instruction caused an error. ignne# has no effect when the ne bit in control register 0 (cr0) is set. ignne# is an asynchronous signal. however, to ensure recognition of this signal following an input/output write instruction, it must be valid along with the trdy# assertion of the corresponding input/output write bus transaction.
60 datasheet signal name t ype description init# i init# (initialization), when asserted, resets integer registers inside the processor without aff ecting its internal caches or floating - point registers. the processor then begins execution at the power - on reset vector configured during power - on configuration. the processor continues to handle snoop requests during init# assertion. init# is an asynchro nous signal. however, to ensure recognition of this signal following an input/output write instruction, it must be valid along with the trdy# assertion of the corresponding input/output write bus transaction. init# must connect the appropriate pins of both fsb agents. if init# is sampled active on the active to inactive transition of reset#, the processor reverses its fsb data and address signals internally to ease mother board layout for systems where the chipset is on the other side of the mother board. d [63:0] => d[0:63] a[31:3] => a[3:31] dinv[3:0]# is also reversed. lint[1:0] i lint[1:0] (local apic interrupt) must connect the appropriate pins of all apic bus agents. when the apic is disabled, the lint0 signal becomes intr, a maskable interrupt reques t signal, and lint1 becomes nmi, a non - maskable interrupt. intr and nmi are backward compatible with the signals of those names on the pentium processor. both signals are asynchronous. both of these signals must be software configured using bios programmin g of the apic register space to be used either as nmi/intr or lint[1:0]. because the apic is enabled by default after reset, operation of these pins as lint[1:0] is the default configuration. lock# i/o lock# indicates to the system that a transaction must occur automatically. this signal must connect the appropriate pins of both fsb agents. for a locked sequence of transactions, lock# is asserted from the beginning of the first transaction to the end of the last transaction. when the priority agent assert s bpri# to arbitrate for ownership of the fsb, it will wait until it observes lock# deasserted. this enables symmetric agents to retain ownership of the fsb throughout the bus locked operation and ensure the automatic operation of the lock. prdy# o the pr obe ready s ignal used by debug tools to request debug operation of the processor. preq# i probe request s ignal used by debug tools to request debug operation of the processor. prochot# i/o, as an output, prochot# (processor hot) will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature. this indicates that the processor thermal control circuit (tcc) has been activated, if enabled. as an input, assertion of prochot# by th e system will activate the tcc, if enabled. the tcc will remain active until the system de - asserts prochot#.
package mechanical specifications and pin information datasheet 61 signal name t ype description pwrgood i pwrgood (power good) is a processor input. the processor requires this signal to be a clean indication that the clocks and power supplie s are stable and within their specifications. ?clean? implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification. the signal must then transition monotonically to a high state. pwrgood can be driven inactive at any time, but clocks and power must again be stable before a subsequent rising edge of pwrgood. the pwrgood signal must be supplied to the processor ? it is used to protect int ernal circuits against voltage sequencing issues. it should be driven high throughout boundary scan operation. req[4:0]# i/o req[4:0]# (request command) must connect the appropriate pins of both fsb agents. they are asserted by the current bus owner to de fine the currently active transaction type. these signals are source synchronous to adstb[0]#. reset# i asserting the reset# signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents. for a power - on reset, reset# must stay active for at least two milliseconds after v cc and bclk have reached their proper specifications. on observing active reset#, both fsb agents will de - assert their outputs within two clocks. all processor straps must be va lid within the specified setup time before reset# is de - asserted. rs[2:0]# i rs[2:0]# (response status) are driven by the response agent (the agent responsible for completion of the current transaction), and must connect the appropriate pins of both fsb a gents. rsvd reserved rsvd[3:0] pins e10, e8, d7 and d9 must be tied directly to v ccp to ensure proper operation of the processor. all other rsvd signals can be left as no connects. slp# i slp# (sleep), when asserted in stop - grant state, causes the proces sor to enter the sleep state. during sleep state, the processor stops providing internal clock signals to all units, leaving only the phase - locked loop (pll) still operating. processors in this state will not recognize snoops or interrupts. the processor w ill recognize only assertion of the reset# signal, de - assertion of slp#, and removal of the bclk input while in sleep state. if slp# is de - asserted, the processor exits sleep state and returns to stop - grant state, restarting its internal clock signals to t he bus and processor core units. if dpslp# is asserted while in the sleep state, the processor will exit the sleep state and transition to the deep sleep state. smi# i smi# (system management interrupt) is asserted asynchronously by system logic. on accep ting a system management interrupt, the processor saves the current state and enters system management mode (smm). an smi acknowledge transaction is issued, and the processor begins program execution from the smm handler. if smi# is asserted during the de - assertion of reset# the processor will tri - state its outputs.
62 datasheet signal name t ype description stpclk# i stpclk# (stop clock), when asserted, causes the processor to enter a low power stop - grant state. the processor issues a stop - grant acknowledge transaction, and stops providing interna l clock signals to all processor core units except the fsb and apic units. the processor continues to snoop bus transactions and service interrupts while in stop - grant state. when stpclk# is de - asserted, the processor restarts its internal clock to all uni ts and resumes execution. the assertion of stpclk# has no effect on the bus clock ? stpclk# is an asynchronous input. tck i tck (test clock) provides the clock input for the processor test bus (also known as the test access port). tdi i tdi (test data in) transfers serial test data into the processor. tdi provides the serial input needed for jtag specification support. tdo o tdo (test data out) transfers serial test data out of the processor. tdo provides the serial output needed for jtag specification s upport. test[1:4] test signals. all test signals can be left as no connects. thrmtrip# o the processor protects itself from catastrophic overheating by use of an internal thermal sensor. this sensor is set well above the normal operating temperature t o ensure that there are no false trips. the processor will stop all execution when the junction temperature exceeds approximately 120c. this condition is signaled to the system by the thermtrip# (thermal trip) pin. thrmda pwr thermal diode ? anode thrm dc pwr thermal diode ? cathode tms i tms (test mode select) is a jtag specification support signal used by debug tools. trdy# i trdy# (target ready) is asserted by the target to indicate that it is ready to receive a write or implicit writeback data tra nsfer. trdy# must connect the appropriate pins of both fsb agents. trst# i trst# (test reset) resets the test access port (tap) logic. trst# must be driven low during power on reset. v cca pwr v cca provides isolated power for the internal processor core plls. v cc pwr processor core power supply v ss gnd processor core ground node. v ss /nctf gnd non critical to function
package mechanical specifications and pin informatio n datasheet 63 signal name t ype description vid[6:0] o vid[6:0] (voltage id) pins are used to support automatic selection of power supply voltages (v cc ). unlike some previous gene rations of processors, these are cmos signals that are driven by the processor. the voltage supply for these pins must be valid before the vr can supply v cc to the processor. conversely, the vr output must be disabled until the voltage supply for the vid p ins becomes valid. the vid pins are needed to support the processor voltage specification variations. see table 3 for definitions of these pins. the vr must supply the voltage that is requested by the pins, or disable itself. v ccp pwr processor i/o power supply which needs to remain on in deep power down technology (c6) state. v ccp c6 pwr processor i/o power supply which needs to remain on in deep power down technology (c6) state. v cc_sense o vcc_ sense is an isolated low impedan ce connection to the processor core power (v cc ). it can be used to sense or measure power near the silicon with little noise. v ss_sense o v ss_sense is an isolated low impedance connection to processor core v ss . it can be used to sense or measure ground n ear the silicon with little noise.
64 datasheet this page intentionally left blank.
thermal specifications and design considerations datasheet 65 5 thermal specifications and design considerations the processor requires a thermal solution to maintain temperatures within operating limits as set forth in section 5.1 . any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components in the system. as processor technology changes, thermal management become s increasingly crucial when building computer systems. maintaining the p roper thermal environment is critical to reliable, long - term system operation. a complete thermal solution includes both component and system level thermal management features. compone nt level thermal solutions include active or passive heat spreaders or heat exchangers attached to the exposed processor die. the solution should make firm contact to the die while maintaining processor mechanical specifications such as pressure. a typical system level thermal solution may consist of a system fan used to evacuate or pull air through the system in conjunction with a multi - component heat spreader used to reduce the temperature of the processor and other components while maintaining as uniform a skin temperature as possible. alternatively, the processor may be in a fan - less system, but would likely still use a multi - component heat spreader. note: trading thermal solutions also involves trading performance. to allow for the optimal operation and lon g - term reliability of intel processor - based systems, the system/processor thermal solution should be designed such that the processor remains within the minimum and maximum junction temperature (t j ) specifications at the corresponding thermal design power (tdp) value listed in table 16 and table 17 . thermal solutions not designed to provide this level of thermal capability may affect the long - term relia bility of the processor and system. r efer to the intel centrino atom platform thermal application note document for more details on processor and system level cooling approaches. the maximum junction temperature is defined by an activation of the processor intel thermal monitor. refer to sect ion 5.1.2 for more details. analysis indicates that real applications are unlikely to cause the processor to consume the theoretical maximum power dissipation for sustained time periods. intel recommends that complete thermal solution designs target the tdp indicated in table 16 and table 17 . the intel thermal monitor feature is designed to help protect the processor in the unlikely event that an application exceeds the tdp recommendation for a sustained period of time. for more details on the usage of this feature, refer to section 5.1.2 . in all cases the intel thermal monitor feature must be enabled for the processor to remain within specification.
66 datasheet table 16 . power specifications for intel? atom ? processor s z560, z550, z540, z530, Z520, and z510 symbol proc essor number core frequency and voltage thermal design power unit notes tdp z510 1.1 ghz and hfm v cc 0.6 ghz and lfm v cc 2.0 w w @ 90 c 1, 4 Z520 1.33 ghz and hfm v cc 0.8 ghz and lfm v cc 2.0 w 2.2 w with ht enabled w @ 90 c 1, 4 , 6 z530 1.60 ghz and hfm v cc 0.8 ghz and lfm v cc 2.0 w 2.2 w with ht enabled w @ 90 c 1, 4 , 6 z540 1.86 ghz and hfm v cc 0.8 ghz and lfm v cc 2.4 w 2.64 w with ht enabled w @ 90 c 1, 4 , 6 z550 2 . 00 ghz and hfm v cc 0.8 ghz and lfm v cc 2.4 w 2.64 w with ht enabled w @ 90 c 1, 4 , 6 z560 2 . 13 ghz and hfm v cc 0.8 ghz and lfm v cc 2. 5 w 2.75 w with ht enabled w @ 90 c 1, 4 , 6 symbol parameter min. typ. max. unit notes p ah , p sgnt auto halt, stop grant power @ hfm v cc @ lfm v cc ? ? 1.0 0.7 w w @ 70 c 2 p dprslp deeper slee p power ? ? 0.5 w @ 50 c 2, 5 p dc6 deep power down technology (c6) ? ? 0.1 w @ 50 c 2 t j junction temperature 0 ? 90 c 3, 4 notes: 1. the tdp specification should be used to design the processor thermal solution. the tdp is not the maximum theoretical power t he processor can generate. 2. not 100% tested. these power specifications are determined by characterization of the processor currents at higher temperatures and extrapolating the values for the temperature indicated. 3. as measured by the activation of the on - die intel thermal monitor. the intel thermal monitor?s automatic mode is used to indicate that the maximum t j has been reached. refer to section 5.1 for more details. 4. the intel thermal monitor automatic mode must be enabled for the processor to operate within specifications. 5. deep sleep state is mapped to deeper sleep state. 6. intel hyper - threading technology requires a computer system with an intel processor supporting hyper - threading technology and an ht technology enabled chipset, bios and operating system. hyper - threading technology is available on select intel atom? processor components (Z520, z530, z540 , z550 , and z560 ). ht technology can add 2 00 mw of power above tdp.
thermal specifications and design considerations datasheet 67 table 17 . power specifications for intel ? atom ? processor s z515 and z500 symbol processor number core frequency and voltage thermal design power unit notes tdp z500/z515 z500/z515 0.8 ghz and hfm v cc 0.6 ghz and lfm v cc 0. 65 w @ 90 c 1, 4, 6, 7 symbol parameter min. typ. max. unit notes p ah , p sgnt auto halt, stop grant power @ hfm v cc @ lfm v cc ? ? ? ? 0.6 0.5 w w @ 70 c 2, 6, 7 p dprslp deeper sleep power ? ? 0.3 w 2, 5 p dc6 deep power down tech nology (c6) ? ? 0.08 w 2 t j junction temperature 0 ? 90 c 3, 4 notes: 1. the tdp specification should be used to design the processor thermal solution. the tdp is not the maximum theoretical power the processor can generate. 2. not 100% tested. these power specifi cations are determined by characterization of the processor currents at higher temperatures and extrapolating the values for the temperature indicated. 3. as measured by the activation of the on - die intel thermal monitor. the intel thermal monitor?s automatic mode is used to indicate that the maximum t j has been reached. refer to section 5.1 for more details. 4. the intel thermal monitor automatic mode must be enabled for the processor to operate within specifications. 5. deep sleep state is mapped to deeper sleep state. 6. intel atom processor z515 enables inte l? burst performance technology. 7. i ntel? ht technology requires a computer system with an intel processor supporting hyper - threading technology and an intel ? ht technology enabled chipset, bios , and operating system. the intel atom processor z500 does not support intel ? ht technology while the intel atom processor z515 does support intel ? ht technology.
68 datasheet 5.1 thermal specifications the processor incorporates three methods of monitoring die temperature ? digital thermal sensor, intel thermal monitor, and the thermal diode. the intel thermal monitor (detailed in section 5.1.2 ) must be used to determine when the maximum specified processor junction temperature has been reached. 5.1.1 thermal diode the processor incorporates an on - die pnp transistor whose base emit ter junction is used as a thermal ?diode?, with its collector shorted to ground. the thermal diode can be read by an off - die analog/digital converter (a thermal sensor) located on the motherboard or a stand - alone measurement kit. the thermal diode may be u sed to monitor the die temperature of the processor for thermal management or instrumentation purposes but is not a reliable indication that the maximum operating temperature of the processor has been reached. when using the thermal diode, a temperature of fset value must be read from a processor msr and applied. see section 5.1.2 for more details. see section 5.1.3 for thermal diode usage recommendation when the prochot# signal is no t asserted. the reading of the external thermal sensor (on the motherboard) connected to the processor thermal diode signals will not necessarily reflect the temperature of the hottest location on the die. this is due to inaccuracies in the external therma l sensor, on - die temperature gradients between the location of the thermal diode and the hottest location on the die, and time based variations in the die temperature measurement. time based variations can occur when the sampling rate of the thermal diode (by the thermal sensor) is slower than the rate at which the t j temperature can change. offset between the thermal diode based temperature reading and the intel thermal monitor reading may be characterized using the intel thermal monitor?s automatic mode activation of the thermal control circuit. this temperature offset must be taken into account when using the processor thermal diode to implement power management events. this offset is different than the diode t offset value programmed into the processor m odel specific register (msr). table 18. and table 19 provide the diode interface and specifications. transistor model parameters shown in table 19 provide more accurate temperatu re measurements when the diode ideality factor is closer to the maximum or minimum limits. contact your external sensor supplier for their recommendation. the thermal diode is separate from the thermal monitor?s thermal sensor and cannot be used to predict the behavior of the thermal monitor.
thermal specifications and design considerations datasheet 69 table 18 . thermal diode interface signal name pin/ball number signal description thermda t5 thermal diode anode thermdc u4 thermal diode cathode table 19 . thermal diod e parameters using transistor model symbol parameter min. typ. max. unit note s ifw forward bias current 5 ? 200 a 1 ie emitter current 5 ? 200 a 1 nq transistor ideality 0.997 1.001 1.015 2, 3, 4 beta 0.25 ? 0.65 2, 3 r t series resistance 2.79 4.52 6.24 ? 2, 5 notes: 1. intel does not support or recommend operation of the thermal diode under reverse bias. 2. characte rized across a temperature range of 50 ? 100 c. 3. not 100% tested. specified by design characterization. 4. the ideality factor, nq, represents the deviation from ideal transistor model behavior as exemplified by the equation for the collector current: i c = i s * (e qv be /n q kt ? 1) w here i s = saturation current, q = electronic charge, v be = voltage across the transistor base emitter junction (same nodes as vd), k = boltzmann constant, and t = absolute temperature (kelvin). 5. the series resistance, r t , provided in the diode model table ( table 19 ) can be used for more accurate readings as needed. when calculating a temperature based on the thermal diode measurements, a number of parameters must be either measured or assumed. most devices m easure the diode ideality and assume a series resistance and ideality trim value, although are capable of also measuring the series resistance. calculating the temperature is then accomplished using the equation listed under table 19 . in most sensing devices, an expected value for the diode ideality is designed - in to the temperature calculation equation. if the designer of the temperature sensing device assumes a perfect diode, the ideality value (also called n trim ) will be 1.000. given that most diodes are not perfect, the designers usually select an n trim value that more closely matches the behavior of the diodes in the processor. if the processor diode ideality deviates from that of the n trim , each calculated temperature will be offset by a fixed amount. this temperature offset can be calculated with the equation: t error (nf) = tmeasured * (1 ? n actual /n trim ) w here t error(nf) is the offset in degrees c, t measured is in kelvin, n actual is the measured ideality of the diode, and n tri m is the diode ideality assumed by the temperature sensing device.
70 datasheet 5.1.2 intel ? thermal monitor the intel thermal monitor helps control the processor temperature by activating the tcc (thermal control circuit) when the processor silicon reaches its maximum opera ting temperature. the temperature at which the intel thermal monitor activates the tcc is not user configurable. bus traffic is snooped in the normal manner and interrupt requests are latched (and serviced during the time that the clocks are on) while the tcc is active. with a properly designed and characterized thermal solution, it is anticipated that the tcc would only be activated for very short periods of time when running the most power intensive applications. the processor performance impact due to th ese brief periods of tcc activation is expected to be minor and hence not detectable. an under - designed thermal solution that is not able to prevent excessive activation of the tcc in the anticipated ambient environment may cause a noticeable performance loss and may affect the long - term reliability of the processor. in addition, a thermal solution that is significantly under designed may not be capable of cooling the processor even when the tcc is active continuously. the intel thermal monitor controls th e processor temperature by modulating (starting and stopping) the processor core clocks or by initiating an enhanced intel speedstep technology transition when the processor silicon reaches its maximum operating temperature. the intel thermal monitor uses two modes to activate the tcc: automatic mode and on - demand mode. if both modes are activated, automatic mode takes precedence. there are two automatic modes called intel thermal monitor 1 (tm1) and intel thermal monitor 2 (tm2). these modes are selected by writing values to the msrs of the processor. after automatic mode is enabled, the tcc will activate only when the internal die temperature reaches the maximum allowed value for operation. the intel thermal monitor automatic mode must be enabled through bios for the processor to be operating within specifications. intel recommends tm1 and tm2 be enabled on the processor. when tm1 is enabled and a high temperature situation exists, the clocks will be modulated by alternately turning the clocks off and on at a 50% duty cycle. cycle times are processor speed dependent and will decrease linearly as processor core frequencies increase. once the temperature has returned to a non - critical level, modulation ceases and tcc goes inactive. a small amount of hysteres is has been included to prevent rapid active/inactive transitions of the tcc when the processor temperature is near the trip point. the duty cycle is factory configured and cannot be modified. also, automatic mode does not require any additional hardware, software drivers, or interrupt handling routines. processor performance will be decreased by the same amount as the duty cycle when the tcc is active. when tm2 is enabled and a high temperature situation exists, the processor will perform an enhanced inte l speedstep technology transition to the lfm. when the processor temperature drops below the critical level, the processor will make an enhanced intel speedstep technology transition to the last requested operating point. the intel thermal monitor automat ic mode must be enabled through bios for the processor to be operating within specifications. intel recommends tm1 and tm2 be enabled on the processors. tm1 and tm2 can co - exist within the processor. if both tm1 and tm2 bits are enabled in the auto - throttl e msr, tm2 will take precedence over tm1. however, if force tm1
thermal specifications and design considerations datasheet 71 over tm2 is enabled in msrs using bios and tm2 is not sufficient to cool the processor below the maximum operating temperature, then tm1 will also activate to help cool down the processor. if a processor load based enhanced intel speedstep technology transition (through msr write) is initiated when a tm2 period is active, there are two possible results: ? if the processor load based enhanced intel speedstep technology transition target frequency is higher than the tm2 transition based target frequency, the processor load - based transition will be deferred until the tm2 event has been completed. ? if the processor load - based enhanced intel speedstep technology transition target frequency is lower tha n the tm2 transition based target frequency, the processor will transition to the processor load - based enhanced intel speedstep technology target frequency point. the tcc may also be activated using on - demand mode. if bit 4 of the acpi intel thermal monito r control register is written to a 1, the tcc will be activated immediately independent of the processor temperature. when using on - demand mode to activate the tcc, the duty cycle of the clock modulation is programmable using bits 3:1 of the same acpi inte l thermal monitor control register. in automatic mode, the duty cycle is fixed at 50% on, 50% off, however in on - demand mode, the duty cycle can be programmed from 12.5% on/ 87.5% off, to 87.5% on/12.5% off in 12.5% increments. on - demand mode may be used a t the same time automatic mode is enabled ? however, if the system tries to enable the tcc using on - demand mode at the same time automatic mode is enabled and a high temperature condition exists, automatic mode will take precedence. an external signal, proc hot# (processor hot) is asserted when the processor detects that its temperature is above the thermal trip point. bus snooping and interrupt latching are also active while the tcc is active. besides the thermal sensor and thermal control circuit, the inte l thermal monitor also includes one acpi register, one performance counter register, three msr, and one i/o pin (prochot#). all are available to monitor and control the state of the intel thermal monitor feature. the intel thermal monitor can be configured to generate an interrupt upon the assertion or de - assertion of prochot#. prochot# will not be asserted when the processor is in the stop grant, sleep, deep sleep, and deeper sleep low power states ? hence, the thermal diode reading must be used as a safegu ard to maintain the processor junction temperature within maximum specification. if the platform thermal solution is not able to maintain the processor junction temperature within the maximum specification, the system must initiate an orderly shutdown to p revent damage. if the processor enters one of the above low power states with prochot# already asserted, prochot# will remain asserted until the processor exits the low power state and the processor junction temperature drops below the thermal trip point. if intel thermal monitor automatic mode is disabled, the processor will operate out of specification. regardless of enabling the automatic or on - demand modes, in the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached a temperature of approximately 120 c. at this point the thermtrip# signal will go active. thermtrip# activation is independent of processor activity and does not generate any bus cycles. when thermtrip# is asserted, the processor c ore voltage must shut down within the time specified in chapter 0 .
72 datasheet 5.1.3 digital thermal sensor the processor also contains an on die digital thermal sensor (dts) that is read using an msr (no i/o interface). the processor has a unique digital thermal sensor that?s temperature is accessible using the processor msrs. the dt s is the preferred method of reading the processor die temperature since it can be located much closer to the hottest portions of the die and can thus more accurately track the die temperature and potential activation of processor core clock modulation usi ng the thermal monitor. the dts is only valid while the processor is in the normal operating state (the normal package level low power state). unlike traditional thermal devices, the dts outputs a temperature relative to the maximum supported operating tem perature of the processor (t j_max ). it is the responsibility of software to convert the relative temperature to an absolute temperature. the temperature returned by the dts will always be at or below t j_max . catastrophic temperature conditions are detectab le using an out of spec status bit. this bit is also part of the dts msr. when this bit is set, the processor is operating out of specification and immediate shutdown of the system should occur. the processor operation and code execution is not ensured onc e the activation of the ?out of spec? status bit is set. the dts - relative temperature readout corresponds to the thermal monitor (tm1/tm2) trigger point. when the dts indicates maximum processor core temperature has been reached, the tm1 or tm2 hardware t hermal control mechanism will activate. the dts and tm1/tm2 temperature may not correspond to the thermal diode reading since the thermal diode is located in a separate portion of the die and thermal gradient from the core dts. additionally, the thermal gr adient from dts to thermal diode can vary substantially due to changes in processor power, mechanical and thermal attach, and software application. the system designer is required to use the dts to ensure proper operation of the processor within its temper ature operating specifications. changes to the temperature can be detected using two programmable thresholds located in the processor msrs. these thresholds have the capability of generating interrupts using the core's local apic. refer to the intel ? 64 an d ia - 32 architectures software developer's manuals for specific register and programming details. 5.1.4 out of specification detection overheat detection is performed by monitoring the processor temperature and temperature gradient. this feature is intended for graceful shut down before the thermtrip# is activated. if the processor?s tm1 or tm2 are triggered and the temperature remains high, an ?out of spec? status and sticky bit are latched in the status msr register and generates thermal interrupt . 5.1.5 prochot# si gnal pin an external signal, prochot# (processor hot), is asserted when the processor die temperature has reached its maximum operating temperature. if tm1 or tm2 is enabled, then the tcc will be active when prochot# is asserted. the processor can be confi gured to generate an interrupt upon the assertion or de - assertion of prochot#. refer to the intel ? 64 and ia - 32 architectures software developer's manuals .
thermal specifications and design considera tions datasheet 73 the processor implements a bidirectional prochot# capability to allow system designs to protect vari ous components from overheating situations. the prochot# signal is bidirectional in that it can either signal when the processor has reached its maximum operating temperature or be driven from an external source to activate the tcc. the ability to activate the tcc using prochot# can provide a means for thermal protection of system components. only a single prochot# pin exists at a package level of the processor. when the core's thermal sensor trips, the prochot# signal is driven by the processor package. if only tm1 is enabled, prochot# will be asserted and only the core that is above tcc temperature trip point will have its core clocks modulated. if tm2 is enabled and the core is above tcc temperature trip point, it will enter the lowest programmed tm2 perf ormance state. it is important to note that intel recommends both tm1 and tm2 to be enabled. when prochot# is driven by an external agent, if only tm1 is enabled on the core, then the processor core will have the clocks modulated. if tm2 is enabled, then t he processor core will enter the lowest programmed tm2 performance state. it should be noted that force tm1 on tm2, enabled using bios, does not have any effect on external prochot#. if prochot# is driven by an external agent when tm1, tm2, and force tm1 o n tm2 are all enabled, then the processor will still apply only tm2. prochot# may be used for thermal protection of voltage regulators (vr). system designers can create a circuit to monitor the vr temperature and activate the tcc when the temperature limit of the vr is reached. by asserting prochot# (pulled - low) and activating the tcc, the vr will cool down as a result of reduced processor power consumption. bidirectional prochot# can allow vr thermal designs to target maximum sustained current instead of m aximum current. systems should still provide proper cooling for the vr and rely on bidirectional prochot# only as a backup in case of system cooling failure. the system thermal design should allow the power delivery circuitry to operate within its temperat ure specification even while the processor is operating at its tdp. with a properly designed and characterized thermal solution, it is anticipated that bidirectional prochot# would only be asserted for very short periods of time when running the most power intensive applications. an under - designed thermal solution that is not able to prevent excessive assertion of prochot# in the anticipated ambient environment may cause a noticeable performance loss.

▲Up To Search▲

Price & Availability of Z520

	To Download Z520 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .